SH7059 Datasheet, PDF (706/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

22. Pin Function Controller (PFC)
PKnIR
0
1
Note: n = 15 to 0
Description
Value is not inverted
Value is inverted
(Initial value)
22.3.23 Port L IO Register (PLIOR)
Bit: 15
—
Initial value: 0
R/W: R
14
13
12
11
10
9
8
—
PL13 PL12 PL11 PL10 PL9
PL8
IOR
IOR
IOR
IOR
IOR
IOR
0
0
0
0
0
0
0
R
R/W R/W R/W R/W R/W R/W
Bit: 7
6
5
4
3
2
1
0
PL7
PL6
PL5
PL4
PL3
PL2
PL1
PL0
IOR
IOR
IOR
IOR
IOR
IOR
IOR
IOR
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
The port L IO register (PLIOR) is a 16-bit readable/writable register that selects the input/output direction of the 14 pins in
port L. Bits PL13IOR to PL0IOR correspond to pins PL13/IRQOUT/SCS1 to PL0/TI10. PLIOR is enabled when port L
pins function as general input/output pins (PL13 to PL0), timer input/output pins (TIO11A, TIO11B), or serial clock pins
(SCK2, SCK3, SCK4, SSCK1), and disabled otherwise.
When port L pins function as PL13 to PL0, TIO11A and TIO11B, or SCK2, SCK3, SCK4, and SSCK1, a pin becomes an
output when the corresponding bit in PLIOR is set to 1, and an input when the bit is cleared to 0.
PLIOR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in
software standby mode. It is not initialized in sleep mode.
22.3.24 Port L Control Registers H and L (PLCRH, PLCRL)
Port L control registers H and L (PLCRH, PLCRL) are 16-bit readable/writable registers that select the functions of the 14
multiplex pins in port L. PLCRH selects the functions of the pins for the upper 6 bits of port L, and PLCRL selects the
functions of the pins for the lower 8 bits.
PLCRH and PLCRL are initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware
standby mode, and in software standby mode. They are not initialized in sleep mode.
Rev.3.00 Mar. 12, 2008 Page 616 of 948
REJ09B0177-0300