SH7059 Datasheet, PDF (420/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

12. Advanced Pulse Controller (APC)
• Bits 15 to 8—PULS7 to PULS0 Reset Output Enable (PULS7ROE to PULS0ROE): These bits enable or disable 0
output to the APC pulse output pins (PULS7 to PULS0) bit by bit.
Bits 15 to 8:
PULS7ROE to PULS0ROE
0
1
Description
0 output to APC pulse output pin (PULS7—PULS0) is disabled
0 output to APC pulse output pin (PULS7—PULS0) is enabled
(Initial value)
When one of these bits is set to 1, 0 is output from the corresponding pin on a compare-match between the GR11B and
TCNT11 values.
• Bits 7 to 0—PULS7 to PULS0 Set Output Enable (PULS7SOE to PULS0SOE): These bits enable or disable 1 output
to the APC pulse output pins (PULS7 to PULS0) bit by bit.
Bits 7 to 0:
PULS7SOE to PULS0SOE
0
1
Description
1 output to APC pulse output pin (PULS7—PULS0) is disabled
1 output to APC pulse output pin (PULS7—PULS0) is enabled
(Initial value)
When one of these bits is set to 1, 1 is output from the corresponding pin on a compare-match between the GR11A and
TCNT11 values.
12.3 Operation
12.3.1 Overview
APC pulse output is enabled by designating multiplex pins for APC pulse output with the pin function controller (PFC),
and setting the corresponding bits to 1 in the pulse output port control register (POPCR).
When general register 11A (GR11A) in the advanced timer unit II (ATU-II) subsequently generates a compare-match
signal, 1 is output from the pins set to 1 by bits 7 to 0 in POPCR. When general register 11B (GR11B) generates a
compare-match signal, 0 is output from the pins set to 1 by bits 15 to 8 in POPCR.
0 is output from the output-enabled state until the first compare-match occurs.
The advanced pulse controller output operation is shown in figure 12.2.
Rev.3.00 Mar. 12, 2008 Page 330 of 948
REJ09B0177-0300