SH7059 Datasheet, PDF (91/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 1 Overview
1. Overview
1.1 Features
This LSI is a single-chip RISC microcontroller that integrates a RISC CPU core using an original Renesas architecture
with peripheral functions required for system configuration.
The CPU has a RISC-type instruction set. Basic instructions can be executed in one state (one system clock cycle), which
greatly improves instruction execution speed. In addition, the 32-bit internal architecture enhances data processing power.
With this CPU, it has become possible to assemble low-cost, high-performance/high-functionality systems even for
applications such as real-time control, which could not previously be handled by microcontrollers because of their high-
speed processing requirements.
In addition, this LSI includes on-chip peripheral functions necessary for system configuration, such as a floating-point unit
(FPU) , ROM , RAM, a direct memory access controller (DMAC), timers, a serial communication interface (SCI),
controller area network-II (HCAN-II), A/D converter, interrupt controller (INTC), and I/O ports.
ROM and SRAM can be directly connected by means of an external memory access support function, greatly reducing
system cost.
On-chip ROM is available as flash memory in the F-ZTAT* (Flexible Zero Turn Around Time) version. The flash
memory can be programmed with a programmer that supports this LSI programming, and can also be programmed and
erased by software. Since the programming/erasing control program is included as firmware, programming and erasing
can be performed by calling this program with a user program. This enables the chip to be programmed by the user while
mounted on a board.
The features of this LSI are summarized in table 1.1.
Note: * F-ZTAT is a trademark of Renesas Technology, Corp.
Rev.3.00 Mar. 12, 2008 Page 1 of 948
REJ09B0177-0300