SH7059 Datasheet, PDF (460/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

15. Serial Communication Interface (SCI)
Table 15.7 Maximum Bit Rates during External Clock Input (Clock Synchronous Mode)
Pφ (MHz)
10
12
14
16
18
20
External Input Clock (MHz)
1.6667
2.0000
2.3333
2.6667
3.0000
3.3333
Maximum Bit Rate (Bits/s)
1666666.7
2000000.0
2333333.3
2666666.7
3000000.0
3333333.3
15.2.9 Serial Direction Control Register (SDCR)
Bit:
7
6
5
4
3
2
1
0
–
–
–
–
DIR
–
–
–
Initial value:
1
1
1
1
0
0
1
0
R/W:
R
R
R
R
R/W
R
R
R
The DIR bit in the serial direction control register (SDCR) selects LSB-first or MSB-first transfer. With an 8-bit data
length, LSB-first/MSB-first selection is available regardless of the communication mode. With a 7-bit data length, LSB-
first transfer must be selected. The description in this section assumes LSB-first transfer.
The CPU can always read from SDCR. The CPU should only write to SDCR when making initial settings. Do not use the
CPU to write to SDCR during transmit, receive, or transmit/receive operation.
SDCR is initialized to H'F2 by a power-on reset and in the hardware standby mode. The value is not retained in software
standby mode and it is initialized after release. It is not initialized by a manual reset.
• Bits 7–4—Reserved: The write value should always be 1. If 0 is written to these bits, correct operation cannot be
guaranteed.
• Bit 3—Data Transfer Direction (DIR): Selects the serial/parallel conversion format. Valid for an 8-bit transmit/receive
format.
Bit 3: DIR
0
1
Description
TDR contents are transmitted in LSB-first order
Receive data is stored in RDR in LSB-first order
TDR contents are transmitted in MSB-first order
Receive data is stored in RDR in MSB-first order
(Initial value)
• Bit 2—Reserved: The write value should always be 0. If 1 is written to this bit, correct operation cannot be guaranteed.
• Bit 1—Reserved: This bit is always read as 1, and cannot be modified.
• Bit 0—Reserved: The write value should always be 0. If 1 is written to this bit, correct operation cannot be guaranteed.
15.2.10 Inversion of SCK Pin Signal
The signal input from the SCK pin and the signal output from the SCK pin can be inverted by means of a port control
register setting. See section 22, Pin function Controller (PFC), for details.
Rev.3.00 Mar. 12, 2008 Page 370 of 948
REJ09B0177-0300