SH7059 Datasheet, PDF (130/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

2. CPU
Table 2.11 shows the format used in tables 2.12 to 2.19, which list instruction codes, operation, and execution states in
order by classification.
Table 2.11 Instruction Code Format
Item
Format
Explanation
Instruction
OP.Sz SRC,DEST
OP: Operation code
Sz: Size (B: byte, W: word, or L: longword)
SRC: Source
DEST: Destination
Rm: Source register
Rn: Destination register
imm: Immediate data
disp: Displacement*¹
Instruction code
MSB ↔ LSB
mmmm: Source register
nnnn: Destination register
0000: R0
0001: R1
⋅
⋅
⋅
1111: R15
iiii: Immediate data
dddd: Displacement
Operation
→, ←
Direction of transfer
(xx)
Memory operand
M/Q/T
Flag bits in the SR
&
Logical AND of each bit
|
Logical OR of each bit
^
Exclusive OR of each bit
~
Logical NOT of each bit
<<n
n-bit left shift
>>n
Execution cycles
—
n-bit right shift
Value when no wait states are inserted*²
T bit
—
Value of T bit after instruction is executed. An em-dash (—) in the
column means no change.
Notes: 1. Depending on the operand size, displacement is scaled ×1, ×2, or ×4. For details, see the SH-2E Software
Manual.
2. Instruction execution cycles: The execution cycles shown in the table are minimums. The actual number of
cycles may be increased when (1) contention occurs between instruction fetches and data access, or (2) when
the destination register of the load instruction (memory → register) and the register used by the next instruction
are the same.
Rev.3.00 Mar. 12, 2008 Page 40 of 948
REJ09B0177-0300