SH7059 Datasheet, PDF (386/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

11. Advanced Timer Unit-II (ATU-II)
Channel 10 can also perform compare-match operation by means of the multiplied clock (AGCK1) using general register
10G (GR10G) and 16-bit free-running counter 10G (TCNT10G). TCNT10G is incremented unconditionally by AGCK1.
By making the appropriate setting in the interrupt enable register (TIER), an interrupt request can be sent to the CPU when
TCNT10G and GR10G match. The timing of this interrupt can be selected with the IREG bit in TIER as either on
occurrence of the compare-match or on input of the first TI10 edge after the compare-match.
TCNT10C operation is shown in figure 11.30, and TCNT10G compare-match operation in figure 11.31.
Pφ
STR10
AGCK
ICR10A
Shifter output
RLD10C
RLD10C write
enable signal
00000000
1ck
0000
0002
Initial value set by software
Not loaded when
RLDEN = 1
00000020
1ck
0001
0001
TCNT10C
0001
RLD10C load
signal
AGCK1
RLDEN
0002
0001
0002
0001
0002
0001
0001
0001
0001
RLDEN set to 1
by software
RLDEN set to 0
by software
Figure 11.30 TCNT10C Operation
Note: In case of multiplication factor of 32
Pφ
AGCK
AGCK1
TCNT10G
Write by software
0000
0001
0002
0034
0035
0036
Cleared by AGCK
0000
0001
GR10G
TSR10
CMF10G
TSR10
CMF10G
0034
When IREG = 0
When IREG = 1
Figure 11.31 TCNT10G Compare-Match Operation
Rev.3.00 Mar. 12, 2008 Page 296 of 948
REJ09B0177-0300