SH7059 Datasheet, PDF (440/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

14. Compare Match Timer (CMT)
14.4.2 Compare Match Flag Set Timing
The CMF bit of the CMCSR register is set to 1 by the compare match signal generated when the CMCOR register and the
CMCNT counter match. The compare match signal is generated upon the final state of the match (timing at which the
CMCNT counter matching count value is updated). Consequently, after the CMCOR register and the CMCNT counter
match, a compare match signal will not be generated until a CMCNT counter input clock occurs. Figure 14.4 shows the
CMF bit set timing.
Pφ
CMCNT
input clock
CMCNT
N
0
CMCOR
N
Compare
match signal
CMF
CMI
Figure 14.4 CMF Set Timing
14.4.3 Compare Match Flag Clear Timing
The CMF bit of the CMCSR register is cleared by writing a 0 to it after reading a 1. Figure 14.5 shows the timing when
the CMF bit is cleared by the CPU.
CMCSR write cycle
T1
T2
Pφ
CMF
Figure 14.5 Timing of CMF Clear by the CPU
Rev.3.00 Mar. 12, 2008 Page 350 of 948
REJ09B0177-0300