SH7059 Datasheet, PDF (36/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Differences between SH7058 and SH7058S/SH7059
SH7058 (Rev.3, REJ09B0046-0300H)
SH7058S/SH7059
21.3.16 Port H IO Register (PHIOR)
778
PHIOR is initialized to H'0000 by a power-on reset
(excluding a WDT power-on reset), and in hardware
standby mode. It is not initialized in software standby mode
or sleep mode.
22.3.16 Port H IO Register (PHIOR)
Description amended
PHIOR is initialized to H'0000 by a power-on reset
(excluding a WDT power-on reset), in hardware standby
mode, and in software standby mode. It is not initialized in
sleep mode.
21.3.17 Port H Control Register (PHCR)
779
PHCR is initialized to H'0000 by a power-on reset
(excluding a WDT power-on reset), and in hardware
standby mode. It is not initialized in software standby mode
or sleep mode.
22.3.17 Port H Control Register (PHCR)
Description amended
PHCR is initialized to H'0000 by a power-on reset
(excluding a WDT power-on reset), in hardware standby
mode, and in software standby mode. It is not initialized in
sleep mode.
21.3.18 Port J IO Register (PJIOR)
785
PJIOR is initialized to H'0000 by a power-on reset
(excluding a WDT power-on reset), and in hardware
standby mode. It is not initialized in software standby mode
or sleep mode.
22.3.18 Port J IO Register (PJIOR)
Description amended
PJIOR is initialized to H'0000 by a power-on reset
(excluding a WDT power-on reset), in hardware standby
mode, and in software standby mode. It is not initialized in
sleep mode.
21.3.19 Port J Control Registers H and L (PJCRH, PJCRL)
786
PJCRH and PJCRL are initialized to H'0000 by a power-on
reset (excluding a WDT power-on reset), and in hardware
standby mode. They are not initialized in software standby
mode or sleep mode.
22.3.19 Port J Control Registers H and L (PJCRH, PJCRL)
Description amended
PJCRH and PJCRL are initialized to H'0000 by a power-on
reset (excluding a WDT power-on reset), in hardware
standby mode, and in software standby mode. They are
not initialized in sleep mode.
21.3.20 Port K IO Register (PKIOR)
790
PKIOR is initialized to H'0000 by a power-on reset
(excluding a WDT power-on reset), and in hardware
standby mode. It is not initialized in software standby mode
or sleep mode.
22.3.20 Port K IO Register (PKIOR)
Description amended
PKIOR is initialized to H'0000 by a power-on reset
(excluding a WDT power-on reset), in hardware standby
mode, and in software standby mode. It is not initialized in
sleep mode.
21.3.21 Port K Control Registers H and L (PKCRH,
PKCRL)
790
PKCRH and PKCRL are initialized to H'0000 by a power-on
reset (excluding a WDT power-on reset), and in hardware
standby mode. They are not initialized in software standby
mode or sleep mode.
22.3.21 Port K Control Registers H and L (PKCRH,
PKCRL)
Description amended
PKCRH and PKCRL are initialized to H'0000 by a power-on
reset (excluding a WDT power-on reset), in hardware
standby mode, and in software standby mode. They are
not initialized in sleep mode.
21.3.22 Port K Invert Register (PKIR)
795
PKIR is initialized to H'0000 by a power-on reset (excluding
a WDT power-on reset), and in hardware standby mode. It
is not initialized in software standby mode or sleep mode.
22.3.22 Port K Invert Register (PKIR)
Description amended
PKIR is initialized to H'0000 by a power-on reset (excluding
a WDT power-on reset), in hardware standby mode, and in
software standby mode. It is not initialized in sleep
mode.
Rev.3.00 Mar. 12, 2008 Page xxxvi of xc
REJ09B0177-0300