SH7059 Datasheet, PDF (75/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Contents
Section 1 Overview...........................................................................................................................1
1.1 Features .................................................................................................................................................................. 1
1.2 Block Diagram ....................................................................................................................................................... 7
1.3 Pin Description....................................................................................................................................................... 8
1.3.1 Pin Arrangement ....................................................................................................................................... 8
1.3.2 Pin Functions ............................................................................................................................................ 10
1.3.3 Pin Assignments........................................................................................................................................ 17
Section 2 CPU...................................................................................................................................25
2.1 Register Configuration ........................................................................................................................................... 25
2.1.1 General Registers (Rn).............................................................................................................................. 25
2.1.2 Control Registers ...................................................................................................................................... 26
2.1.3 System Registers ....................................................................................................................................... 27
2.1.4 Floating-Point Registers............................................................................................................................ 27
2.1.5 Floating-Point System Registers ............................................................................................................... 28
2.1.6 Initial Values of Registers......................................................................................................................... 28
2.2 Data Formats .......................................................................................................................................................... 28
2.2.1 Data Format in Registers........................................................................................................................... 28
2.2.2 Data Formats in Memory .......................................................................................................................... 29
2.2.3 Immediate Data Format ............................................................................................................................ 29
2.3 Instruction Features................................................................................................................................................ 29
2.3.1 RISC-Type Instruction Set........................................................................................................................ 29
2.3.2 Addressing Modes .................................................................................................................................... 32
2.3.3 Instruction Format..................................................................................................................................... 35
2.4 Instruction Set by Classification ............................................................................................................................ 37
2.4.1 Instruction Set by Classification ............................................................................................................... 37
2.5 Processing States.................................................................................................................................................... 48
2.5.1 State Transitions........................................................................................................................................ 48
Section 3 Floating-Point Unit (FPU) ................................................................................................51
3.1 Overview................................................................................................................................................................ 51
3.2 Floating-Point Registers and Floating-Point System Registers.............................................................................. 51
3.2.1 Floating-Point Register File ...................................................................................................................... 51
3.2.2 Floating-Point Communication Register (FPUL) ..................................................................................... 51
3.2.3 Floating-Point Status/Control Register (FPSCR)...................................................................................... 52
3.3 Floating-Point Format ............................................................................................................................................ 54
3.3.1 Floating-Point Format............................................................................................................................... 54
3.3.2 Non-Numbers (NaN)................................................................................................................................. 54
3.3.3 Denormalized Number Values.................................................................................................................. 55
3.3.4 Other Special Values................................................................................................................................. 55
3.4 Floating-Point Exception Model ............................................................................................................................ 55
3.4.1 Enable State Exceptions............................................................................................................................ 55
3.4.2 Disable State Exceptions........................................................................................................................... 55
3.4.3 FPU Exception Event and Code................................................................................................................ 56
3.4.4 Floating-Point Data Arrangement in Memory .......................................................................................... 56
3.4.5 Arithmetic Operations Involving Special Operands ................................................................................. 56
3.5 Synchronization with CPU..................................................................................................................................... 56
3.6 Usage Notes ........................................................................................................................................................... 56
Rev.3.00 Mar. 12, 2008 Page lxxv of xc
REJ09B0177-0300