SH7059 Datasheet, PDF (205/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

9. Bus State Controller (BSC)
• Bit 2—CS2 Space Size Specification (A2SZ): Specifies the CS2 space bus size. A 0 setting specifies byte (8-bit) size,
and a 1 setting specifies word (16-bit) size.
Bit 2: A2SZ
0
1
Description
Byte (8-bit) size
Word (16-bit) size
(Initial value)
• Bit 1—CS1 Space Size Specification (A1SZ): Specifies the CS1 space bus size. A 0 setting specifies byte (8-bit) size,
and a 1 setting specifies word (16-bit) size.
Bit 1: A1SZ
0
1
Description
Byte (8-bit) size
Word (16-bit) size
(Initial value)
• Bit 0—CS0 Space Size Specification (A0SZ): Specifies the CS0 space bus size A 0 setting specifies byte (8-bit) size,
and a 1 setting specifies word (16-bit) size.
Bit 0: A0SZ
Description
0
Byte (8-bit) size
1
Word (16-bit) size
(Initial value)
Note: A0SZ is valid only in on-chip ROM enabled mode. In on-chip ROM disabled mode, the CS0 space bus size is
specified by the mode pin.
9.2.2 Bus Control Register 2 (BCR2)
Bit:
Initial value:
R/W:
15
IW31
1
R/W
14
IW30
1
R/W
13
IW21
1
R/W
12
IW20
1
R/W
11
IW11
1
R/W
10
IW10
1
R/W
9
IW01
1
R/W
8
IW00
1
R/W
Bit:
Initial value:
R/W:
7
CW3
1
R/W
6
CW2
1
R/W
5
CW1
1
R/W
4
CW0
1
R/W
3
SW3
1
R/W
2
SW2
1
R/W
1
SW1
1
R/W
0
SW0
1
R/W
BCR2 is a 16-bit readable/writable register that specifies the number of idle cycles and CS signal assert extension of each
CS space.
BCR2 is initialized to H'FFFF by a power-on reset, in hardware standby mode, and in software standby mode. It is not
initialized by a manual reset.
• Bits 15–8—Idles between Cycles (IW31, IW30, IW21, IW20, IW11, IW10, IW01, IW00): These bits specify idle
cycles inserted between consecutive accesses when the second one is to a different CS area after a read. Idles are used
to prevent data conflict between ROM (and other memories, which are slow to turn the read data buffer off), fast
memories, and I/O interfaces. Even when access is to the same area, idle cycles must be inserted when a read access is
followed immediately by a write access. The idle cycles to be inserted comply with the area specification of the
previous access. Refer to section 9.4, Waits between Access Cycles, for details.
Rev.3.00 Mar. 12, 2008 Page 115 of 948
REJ09B0177-0300