SH7059 Datasheet, PDF (721/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

23.7 Port F
Port F is an input/output port with the 16 pins shown in figure 23.6.
23. I/O Ports (I/O)
Port F
ROM disabled ROM enabled
expansion mode expansion mode
PF15 (I/O) /BREQ (input)
PF14 (I/O) /BACK (output)
PF13 (I/O) /CS3 (output)
PF12 (I/O) /CS2 (output)
PF11 (I/O) /CS1 (output)
PF10 (I/O) /CS0 (output)
PF9 (I/O) /RD (output)
PF8 (I/O) /WAIT (input)
PF7 (I/O) /WRH (output)
PF6 (I/O) /WRL (output)
A21 (output)
A20 (output)
PF5 (I/O) /A21 (output) /
POD (input)
PF4 (I/O) /A20 (output)
A19 (output) PF3 (I/O) /A19 (output)
A18 (output) PF2 (I/O) /A18 (output)
A17 (output) PF1 (I/O) /A17 (output)
A16 (output) PF0 (I/O) /A16 (output)
Single-chip mode
PF15 (I/O)/SCS1 (I/O)
PF14 (I/O)/SCS0 (I/O)
PF13 (I/O)
PF12 (I/O)
PF11 (I/O)
PF10 (I/O)
PF9 (I/O)
PF8 (I/O)
PF7 (I/O)
PF6 (I/O)
PF5 (I/O) /POD (input)
PF4 (I/O)
PF3 (I/O)
PF2 (I/O)
PF1 (I/O)
PF0 (I/O)
Figure 23.6 Port F
23.7.1 Register Configuration
The port F register configuration is shown in table 23.11.
Table 23.11 Register Configuration
Name
Abbreviation
R/W
Port F data register
PFDR
R/W
Initial Value
H'0000
Address
H'FFFFF74E
Access Size
8, 16
Rev.3.00 Mar. 12, 2008 Page 631 of 948
REJ09B0177-0300