SH7059 Datasheet, PDF (367/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

11. Advanced Timer Unit-II (ATU-II)
• Bit 2—Noise Canceler Enable (NCE): Enables or disables the noise canceler function.
Bit 2: NCE
0
1
Description
Noise canceler function is disabled
Noise canceler function is enabled
(Initial value)
• Bits 1 and 0—Clock Edge 1 and 0 (CKEG1, CKEG0): These bits select the channel 10 external input (TI10) edge(s).
The clock (AGCK) is generated by the detected edge(s).
Bit 1: CKEG1
0
1
Bit 0: CKEG0
0
1
0
1
Description
TI10 input disabled
TI10 input rising edges detected
TI10 input falling edges detected
TI10 input rising and falling edges both detected
(Initial value)
Timer Status Register 10 (TSR10): TSR10 is a 16-bit readable/writable register that indicates the occurrence of channel
10 input capture or compare-match.
Each flag is an interrupt source, and issues an interrupt request to the CPU if the interrupt is enabled by the corresponding
bit in timer interrupt enable register 10 (TIER10).
TSR10 is initialized to H'0000 by a power-on reset, and in hardware standby mode and software standby mode.
Bit:
15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R
R
Bit:
7
6
5
—
—
—
Initial value:
0
0
0
R/W:
R
R
R
Note: * Only 0 can be written to clear the flag.
4
3
2
1
0
—
CMF10G CMF10B ICF10A CMF10A
0
0
0
0
0
R
R/(W)* R/(W)* R/(W)* R/(W)*
• Bits 15 to 4—Reserved: These bits are always read as 0. The write value should always be 0.
• Bit 3—Compare-Match Flag 10G (CMF10G): Status flag that indicates GR10G compare-match.
Bit 3: CMF10G
0
1
Description
[Clearing condition]
When CMF10G is read while set to 1, then 0 is written to IMF10G
[Setting condition]
When TCNT10G = GR10G
(Initial value)
Rev.3.00 Mar. 12, 2008 Page 277 of 948
REJ09B0177-0300