SH7059 Datasheet, PDF (555/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

17. Controller Area Network-II (HCAN-II)
Bit
Bit Name Initial Value R/W Description
7
TCR7
0
R/W Drift Correction Control
Specifies whether TCNTR is to be incremented by 2 or 0 every time TCNTR
reaches the cycle specified by TDCR. If this function is not required, TDCR
must be set to H'0000.
0: Timer is incremented by 0 (i.e. retains the same value for one clock cycle)
every cycle specified by TDCR.
1: Timer is incremented by 2 every cycle specified by TDCR (see TDCR
description).
6
—
0
⎯ Reserved
Writing 0 to this bit is ignored. The read value is not guaranteed.
5
TCR5
0
R/W HCAN-II Timer Prescaler
4
TCR4
0
3
TCR3
0
2
TCR2
0
1
TCR1
0
0
TCR0
0
R/W Divide the source clock (2 × Pφ) before it is used for the timer. The following
R/W ^{relationship exists between source clocks and the timer}
R/W ^{000000: 1 × source clock}
000001: 2 × source clock
R/W _{000010: 4 × source clock}
R/W _{000011: 6 × source clock}
000100: 8 × source clock
:
111111: 126 × source clock
17.6.3 Timer Status Register_n (TSR_n) (n = 0, 1)
The timer status register (TSR) is a 16-bit read-only register that allows the host CPU to monitor the timer compare match
status and the timer overrun status.
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSR4 TSR3 TSR2 TSR1 TSR0
Initial Value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ R R R R R
Bit
Bit Name
15 to 5 —
4 to 0 TSR[4:0]
Initial Value R/W
0
⎯
0
R
Description
Reserved
Writing 0 to this bit is ignored. The read value is not guaranteed.
These bits are read-only that allow the CPU to monitor the status of the cycle
counter, the timer, and the compare match registers. Writing to these bits is
ignored.
Rev.3.00 Mar. 12, 2008 Page 465 of 948
REJ09B0177-0300