SH7059 Datasheet, PDF (86/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

23.3 Port B ..................................................................................................................................................................... 623
23.3.1 Register Configuration.............................................................................................................................. 623
23.3.2 Port B Data Register (PBDR) ................................................................................................................... 624
23.3.3 Port B Port Register (PBPR)..................................................................................................................... 624
23.4 Port C ..................................................................................................................................................................... 625
23.4.1 Register Configuration.............................................................................................................................. 625
23.4.2 Port C Data Register (PCDR) ................................................................................................................... 626
23.5 Port D..................................................................................................................................................................... 627
23.5.1 Register Configuration.............................................................................................................................. 627
23.5.2 Port D Data Register (PDDR)................................................................................................................... 627
23.5.3 Port D Port Register (PDPR) .................................................................................................................... 628
23.6 Port E ..................................................................................................................................................................... 629
23.6.1 Register Configuration.............................................................................................................................. 629
23.6.2 Port E Data Register (PEDR).................................................................................................................... 630
23.7 Port F...................................................................................................................................................................... 631
23.7.1 Register Configuration.............................................................................................................................. 631
23.7.2 Port F Data Register (PFDR) .................................................................................................................... 632
23.8 Port G..................................................................................................................................................................... 633
23.8.1 Register Configuration.............................................................................................................................. 633
23.8.2 Port G Data Register (PGDR)................................................................................................................... 633
23.9 Port H..................................................................................................................................................................... 634
23.9.1 Register Configuration.............................................................................................................................. 635
23.9.2 Port H Data Register (PHDR)................................................................................................................... 635
23.10 Port J ...................................................................................................................................................................... 636
23.10.1 Register Configuration.............................................................................................................................. 636
23.10.2 Port J Data Register (PJDR) ..................................................................................................................... 637
23.10.3 Port J Port Register (PJPR) ....................................................................................................................... 638
23.11 Port K..................................................................................................................................................................... 638
23.11.1 Register Configuration.............................................................................................................................. 639
23.11.2 Port K Data Register (PKDR)................................................................................................................... 639
23.12 Port L ..................................................................................................................................................................... 640
23.12.1 Register Configuration.............................................................................................................................. 640
23.12.2 Port L Data Register (PLDR).................................................................................................................... 640
23.12.3 Port L Port Register (PLPR) ..................................................................................................................... 641
23.13 POD (Port Output Disable) Control....................................................................................................................... 642
Section 24 ROM (SH7058S) ............................................................................................................ 643
24.1 Features.................................................................................................................................................................. 643
24.2 Overview................................................................................................................................................................ 644
24.2.1 Block Diagram.......................................................................................................................................... 644
24.2.2 Operating Mode ........................................................................................................................................ 645
24.2.3 Mode Comparison..................................................................................................................................... 646
24.2.4 Flash Memory Configuration.................................................................................................................... 646
24.2.5 Block Division .......................................................................................................................................... 647
24.2.6 Programming/Erasing Interface ................................................................................................................ 648
24.3 Pin Configuration................................................................................................................................................... 649
24.4 Register Configuration........................................................................................................................................... 650
24.4.1 Registers ................................................................................................................................................... 650
24.4.2 Programming/Erasing Interface Registers ................................................................................................ 652
24.4.3 Programming/Erasing Interface Parameters ............................................................................................. 656
24.4.4 RAM Emulation Register (RAMER)........................................................................................................ 664
24.5 On-Board Programming Mode .............................................................................................................................. 666
Rev.3.00 Mar. 12, 2008 Page lxxxvi of xc
REJ09B0177-0300