SH7059 Datasheet, PDF (83/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

17.6.8 Cycle Counter Double-Buffer Register n (CCR_buf n) (n = 0, 1) ............................................................ 469
17.6.9 Cycle Maximum Register n (CMAXn) (n = 0, 1) ..................................................................................... 470
17.6.10 Input Capture Registers n (ICR0_cc n, ICR0_buf, ICR0_tm n, ICR1 n) (n = 0, 1) .................................. 470
17.6.11 Timer Compare Match Registers n (TCMR0n, TCMR1n, TCMR2n) (n = 0, 1) ...................................... 472
17.7 Operation................................................................................................................................................................ 473
17.7.1 Test Mode Settings ................................................................................................................................... 473
17.7.2 HCAN Settings ......................................................................................................................................... 474
17.7.3 Message Transmission Sequence.............................................................................................................. 475
17.7.4 Message Transmission Cancellation Sequence......................................................................................... 477
17.7.5 Message Receive Sequence ...................................................................................................................... 478
17.7.6 Reconfiguration of Mailboxes .................................................................................................................. 479
17.7.7 List of Registers ........................................................................................................................................ 481
17.7.8 Interrupt Sources....................................................................................................................................... 482
17.7.9 DMAC Interface ....................................................................................................................................... 483
17.7.10 HCAN-II Port Settings.............................................................................................................................. 484
17.7.11 CAN Bus Interface.................................................................................................................................... 485
17.8 Usage Notes ........................................................................................................................................................... 485
17.8.1 TXPR Setting during Reception................................................................................................................ 485
17.8.2 Transmit Cancellation Setting immediately after Transmission Setting in Bus Idle................................. 486
17.8.3 Failure on Transmit Cancellation at Mailbox 31 ...................................................................................... 487
17.8.4 TXPR Setting during Transmission .......................................................................................................... 487
17.8.5 Time Triggered Transmission Setting/Timer Operation Disabled ............................................................ 488
17.8.6 Mailbox Access during HCAN Sleep Mode ............................................................................................. 489
17.8.7 Notes on Port Settings for 64-Buffer HCAN-II with One Channel .......................................................... 490
Section 18 A/D Converter.................................................................................................................491
18.1 Overview................................................................................................................................................................ 491
18.1.1 Features..................................................................................................................................................... 491
18.1.2 Block Diagram .......................................................................................................................................... 492
18.1.3 Pin Configuration...................................................................................................................................... 494
18.1.4 Register Configuration.............................................................................................................................. 496
18.2 Register Descriptions ............................................................................................................................................. 497
18.2.1 A/D Data Registers 0 to 31 (ADDR0 to ADDR31) .................................................................................. 497
18.2.2 A/D Control/Status Registers 0 and 1 (ADCSR0, ADCSR1) ................................................................... 498
18.2.3 A/D Control Registers 0 to 2 (ADCR0 to ADCR2) .................................................................................. 501
18.2.4 A/D Control/Status Register 2 (ADCSR2)................................................................................................ 502
18.2.5 A/D Trigger Registers 0 to 2 (ADTRGR0 to ADTRGR2) ....................................................................... 504
18.3 CPU Interface......................................................................................................................................................... 505
18.4 Operation................................................................................................................................................................ 506
18.4.1 Single Mode.............................................................................................................................................. 506
18.4.2 Scan Mode ................................................................................................................................................ 507
18.4.3 Analog Input Sampling and A/D Conversion Time.................................................................................. 510
18.4.4 External Triggering of A/D Conversion ................................................................................................... 511
18.4.5 A/D Converter Activation by ATU-II....................................................................................................... 512
18.4.6 ADEND Output Pin .................................................................................................................................. 512
18.5 Interrupt Sources and DMA Transfer Requests ..................................................................................................... 513
18.6 Usage Notes ........................................................................................................................................................... 513
18.6.1 A/D conversion accuracy definitions ........................................................................................................ 514
Rev.3.00 Mar. 12, 2008 Page lxxxiii of xc
REJ09B0177-0300