SH7059 Datasheet, PDF (243/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

10. Direct Memory Access Controller (DMAC)
When address reload is on, the SAR2 value returns to its initially set value every four transfers. In the above example,
when a transfer request is input from the A/D1, the byte-size data is first read in from the H'FFFFF820 register of on-chip
A/D1 and that data is written to internal address H'FFFF6000. Because a byte-size transfer was performed, the SAR2 and
DAR2 values at this point are H'FFFFF821 and H'FFFF6001, respectively. Also, because this is a burst transfer, the bus
right remains secured, so continuous data transfer is possible.
When four transfers are completed, if address reload is off, execution continues with the fifth and sixth transfers and the
SAR2 value continues to increment from H'FFFFF824 to H'FFFFF825 to H'FFFFF826 and so on. However, when address
reload is on, DMAC transfer is halted upon completion of the fourth transfer and the bus right request signal to the CPU is
cleared. At this time, the value stored in SAR2 is not H'FFFFF823 → H'FFFFF824, but H'FFFFF823 → H'FFFFF820, a
return to the initially set address. The DAR2 value always continues to be decremented regardless of whether address
reload is on or off.
The DMAC internal status, due to the above operation after completion of the fourth transfer, is indicated in table 10.7 for
both address reload on and off.
Table 10.7 DMAC Internal Status
Item
Address Reload On
Address Reload Off
SAR2
H'FFFFF820
H'FFFFF824
DAR2
H'FFFF6004
H'FFFF6004
DMATCR2
H'0000007C
H'0000007C
Bus right
Released
Retained
DMAC operation
Halted
Processing continues
Interrupts
Not issued
Not issued
Transfer request source flag clear
Executed
Not executed
Notes: 1. Interrupts are executed until the DMATCR2 value becomes 0, and if the IE bit of CHCR2 is set to 1, are issued
regardless of whether address reload is on or off.
2. If transfer request source flag clears are executed until the DMATCR2 value becomes 0, they are executed
regardless of whether address reload is on or off.
3. Designate burst mode when using the address reload function. There are cases where abnormal operation will
result if it is used in cycle-steal mode.
4. Designate a multiple of four for the DMATCR2 value when using the address reload function. There are cases
where abnormal operation will result if anything else is designated.
To execute transfers after the fifth transfer when address reload is on, have the transfer request source issue another
transfer request signal.
Rev.3.00 Mar. 12, 2008 Page 153 of 948
REJ09B0177-0300