SH7059 Datasheet, PDF (303/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

11. Advanced Timer Unit-II (ATU-II)
• Bit 12—Input Capture/Compare-Match Flag 5C (IMF5C): Status flag that indicates GR5C input capture or compare-
match. The flag is not set in PWM mode.
Bit 12: IMF5C
0
1
Description
[Clearing condition]
When IMF5C is read while set to 1, then 0 is written to IMF5C
(Initial value)
[Setting conditions]
• When the TCNT5 value is transferred to GR5C by an input capture signal while GR5C is
functioning as an input capture register
• When TCNT5 = GR5C while GR5C is functioning as an output compare register
• Bit 11—Input Capture/Compare-Match Flag 5B (IMF5B): Status flag that indicates GR5B input capture or compare-
match. The flag is not set in PWM mode.
Bit 11: IMF5B
0
1
Description
[Clearing condition]
When IMF5B is read while set to 1, then 0 is written to IMF5B
(Initial value)
[Setting conditions]
• When the TCNT5 value is transferred to GR5B by an input capture signal while GR5B is
functioning as an input capture register
• When TCNT5 = GR5B while GR5B is functioning as an output compare register
• Bit 10—Input Capture/Compare-Match Flag 5A (IMF5A): Status flag that indicates GR5A input capture or compare-
match. The flag is not set in PWM mode.
Bit 10: IMF5A
0
1
Description
[Clearing condition]
When IMF5A is read while set to 1, then 0 is written to IMF5A
(Initial value)
[Setting conditions]
• When the TCNT5 value is transferred to GR5A by an input capture signal while GR5A is
functioning as an input capture register
• When TCNT5 = GR5A while GR5A is functioning as an output compare register
• Bit 9—Overflow Flag 4 (OVF4): Status flag that indicates TCNT4 overflow.
Bit 9: OVF4
0
1
Description
[Clearing condition]
When OVF4 is read while set to 1, then 0 is written to OVF4
[Setting condition]
When the TCNT4 value overflows (from H'FFFF to H'0000)
(Initial value)
Rev.3.00 Mar. 12, 2008 Page 213 of 948
REJ09B0177-0300