SH7059 Datasheet, PDF (539/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

17. Controller Area Network-II (HCAN-II)
17.4.6 Interrupt Mask Register_n (IMR_n) (n = 0, 1)
The interrupt mask register (IMR) is a 16-bit register that masks output of corresponding interrupt requests in the interrupt
register (IRR). An interrupt request is masked if the corresponding bit is set to 1. This register can be read or written to at
any time. IMR directly controls the generation of an interrupt request, but does not control the setting of the corresponding
bit in IRR.
• IMR
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IMR15 IMR14 IMR13 IMR12 IMR11 IMR10 IMR9 IMR8 IMR7 IMR6 IMR5 IMR4 IMR3 IMR2 IMR1 IMR0
Initial Value: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
Bit Name Initial Value R/W Description
15
IMR15
1
14
IMR14
1
13
IMR13
1
12
IMR12
1
11
IMR11
1
R/W Mask the corresponding IRR[15:0] interrupts. When this bit is set, the
R/W ^{interrupt signal is masked, although the IRR setting is retained.}
R/W ^{0: Corresponding IRR is not masked (an interrupt request is generated for}
interrupt conditions)
R/W
1: Corresponding IRR interrupt is masked
R/W
10
IMR10
1
R/W
9
IMR9
1
R/W
8
IMR8
1
R/W
7
IMR7
1
R/W
6
IMR6
1
R/W
5
IMR5
1
R/W
4
IMR4
1
R/W
3
IMR3
1
R/W
2
IMR2
1
R/W
1
IMR1
1
R/W
0
IMR0
1
R/W
17.4.7 Transmit Error Counter_n (TEC_n) (n = 0, 1)/
Receive Error Counter_n (REC_n) (n = 0, 1)
The transmit error counter (TEC)/receive error counter (REC) is a 16-bit readable/(writable) register that functions as a
counter indicating the number of transmit/receive message errors on the CAN interface. The count value is stipulated in
the CAN protocol specification (References 2 and 3). In normal mode, this register is read-only, and can only be modified
by the CAN interface. This register can be cleared by a reset request (MCR0) or bus off.
In test mode (i.e. MCR[15] = MCR[14] = 1), it is possible to write to this register. A same value can only be written to
TEC and REC, and the value set in TEC is written to TEC and REC. When writing to this register, the HCAN needs to be
in halt mode. This function is only intended for test purposes.
[Important] While the HCAN-II is in the bus-off status, the TEC and REC values are undefined.
Rev.3.00 Mar. 12, 2008 Page 449 of 948
REJ09B0177-0300