SH7059 Datasheet, PDF (1026/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Appendix A On-chip peripheral module Registers
Reset State
Type
Name
Advanced timer unit-II TIER0, TIER1A, 1B
(ATU-II)
TIER2A, 2B, TIER3,
TIER6-11
TIOR0, TIOR1A-D,
TIOR2A-D, TIOR3A, 3B,
TIOR4A, 4B, TIOR5A, 5B,
TIOR10,11
TMDR
TNCT10E
TRGMDR
TSR0, TSR1A, 1B,
TSR2A, 2B, TSR3,
TSR6-11
TSTR1-3
Advanced pulse
controller (APC)
POPCR
Watchdog timer
(WDT)
TCNT
TCSR
RSTCSR
Serial
communication
interface (SCI)
SMR0 to SMR4
BRR0 to BRR4
SCR0 to SCR4
TDR0 to TDR4
SSR0 to SSR4
RDR0 to RDR4
SDCR0 to SDCR4
Synchronous
Communication
Unit (SSU)
SSCRH_0,1
SSCRL_0,1
SSMR_0,1
SSER_0,1
SSSR_0,1
SSRDR0 to 3_0,1
SSTRSR_0,1
Power-On
Initialized
Initialized
Initialized
Initialized
Initialized
Power-Down State
Hardware
Standby
Software
Standby
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Sleep
Held
Held
Held
Held
Held
Rev.3.00 Mar. 12, 2008 Page 936 of 948
REJ09B0177-0300