SH7059 Datasheet, PDF (403/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

11. Advanced Timer Unit-II (ATU-II)
Sample Setup Procedure for Event Counter Operation: An example of the setup procedure for event counter operation
is shown in figure 11.61.
Start
Set number of events 1
Set port-ATU-II connection 2
Select counter clock 3
1. Set the number of events to be counted in a general register
(GR9A to GR9D). Also, if necessary, an interrupt request
can be sent to the CPU upon compare-match by making a
setting in the timer interrupt enable register (TIER).
2. Set the port control register, corresponding to the port for
signal input to the event counter, to ATU event counter input.
3. Select the event counter count edge with the EGSEL bits in
the channel 9 timer control register (TCR9A to TCR9C).
4. Input a signal to the event counter input pin.
Start event input
4
Event counter operation
Figure 11.61 Sample Setup Procedure for Event Counter Operation
Sample Setup Procedure for Channel 3 Input Capture Triggered by Channel 9 Compare-Match: An example of the
setup procedure for compare-match signal transmission is shown in figure 11.62.
Start
Set port-ATU-II commection 1 _{1. Set the port control register, corresponding to the port for}
signal input to the event counter, to ATU event counter input.
2. Set the channel 3 timer I/O control register (TIOR3A,
Set input capture
TIOR3B), and select the input capture disable setting for the
2 _{general registers (GR3A to GR3D). Input from pins TIO3A to}
TIO3D is masked.
3. Select the event counter count edge with the EGSEL bits in
Select compare-match 3
the channel 9 timer control register (TCR9A, TCR9B), and
set the TRG3xEN bit to 1. Set the timing for capture in the
general register (GR9A to GR9D).
4. Set bit STR3 to 1 in the timer start register (TSTR) to start
Start counter
4 ^{the channel 3 free-running counter (TCNT3).}
5. Input a signal to the event counter input pin.
Start event input
Input capture operation
Note: An interrupt request can be sent to the CPU upon
5
channel 9 compare-match by making a setting in the
timer interrupt enable register (TIER), but an interrupt
request cannot be sent to the CPU upon channel 3 input
capture.
Figure 11.62 Sample Setup Procedure for Compare-Match Signal Transmission
Rev.3.00 Mar. 12, 2008 Page 313 of 948
REJ09B0177-0300