SH7059 Datasheet, PDF (413/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

11. Advanced Timer Unit-II (ATU-II)
Automatic TSR Clearing by DMAC Activation by the ATU: Automatic clearing of TSR is performed after completion
of the transfer when the DMAC is in burst mode, and each time the DMAC returns the bus in cycle steal mode.
Interrupt Status Flag Setting/Resetting: With TSR, a 0 write to a bit is possible even if overlapping events occur for the
same bit before writing 0 after reading 1 to clear that bit. (The duplicate events are not accepted.)
External Output Values in Software Standby Mode and Pin State after Software Standby Mode Release: In
software standby mode, the ATU registers and external output values are initialized. The pin state is high impedance.
Since the settings of the pin function controller (PFC) are initialized, the PFC must be set again to use the function of the
ATU-II external pins after software standby release.
Contention between TCNT Clearing from Channel 10 and TCNT Overflow: When a channel 1 or 2 free-running
counter (TCNT1A, TCNT1B, TCNT2A, TCNT2B) overflows, it is cleared to H'0000. If a clear signal from the channel
10 correction counter clear register (TCCLR) is input at the same time, setting 1 to the overflow interrupt status flag
(OVF) due to the overflow is still performed in the same way as for a normal overflow.
Contention between Channel 10 Reload Register Transfer Timing and Write: If there is contention between a
multiplied-output transfer from the input capture register (ICR10A) to the channel 10 reload register (RLDR10C), and the
timing of a CPU write to that register, the CPU write has priority and the multiplied output is ignored.
Contention between Channel 10 Reload Timing and Write to TCNT10C: If there is contention between a multiplied-
output transfer from the input capture register (ICR10A) to the channel 10 reload register (RLDR10C), and a CPU write to
the reload counter (TCNT10C), the CPU write has priority and the multiplied output is ignored.
ATU Pin Setting: Since input capture or count operation may be occurred when a port is set to the ATU pin function, the
following points must be noted.
When using a port for input capture input, the corresponding TIOR register must be in the input capture disabled state
when the port is set. Regarding channel 10 TI10 input, TCR10 must be in the TI10 input disabled state when the port is
set. When using a port for external clock input, the STR bit for the corresponding channel must be in the count operation
disabled state when the port is set. When using a port for event input, the corresponding TCR register must be in the count
operation disabled state when the port is set.
Regarding TCLKB and TI10 input, although input is assigned to a number of pins, when using TCLKB and TI10 input,
only one pin should be enabled.
Writing to ROM Area Immediately after ATU Register Write: If a write cycle for a ROM address for which address
bit 11 = 0 and address bit 12 = 1 (H'00001000 to H'000017FF, H'00003000 to H'000037FF, H'00005000 to H'000057FF,
..., H'0007F000 to H'0007F7FF, ..., H'000FF000 to H'000FF7FF) occurs immediately after an ATU register write cycle,
the value, or part of the value, written to ROM will be written to the ATU register. The following measures should be
taken to prevent this.
• Do not perform a CPU write to a ROM address immediately after an ATU register write cycle. For example, an
instruction arrangement in which an MOV instruction that writes to the ATU is located at an even-word address (4n
address), and is immediately followed by an MOV instruction that writes to a ROM area, will meet the bug conditions.
• Do not perform an AUD write to any of the above ROM addresses immediately after an ATU register write cycle. For
example, in the case of a write to overlap RAM when using the RAM emulation function, the write should be
performed to the on-chip RAM area address, not the overlapping ROM area address.
• Do not perform a DMAC write to an ATU register when a ROM address write operation occurs.
Rev.3.00 Mar. 12, 2008 Page 323 of 948
REJ09B0177-0300