SH7059 Datasheet, PDF (632/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

20. High-performance User Debug Interface (H-UDI)
20.3.2 Status Register (SDSR)
(SH7058SF)
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value: 0
1
0
1
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit: 7
6
5
4
3
2
1
0
—
—
—
—
—
—
— SDTRF
Initial value: 0
0
0
0
0
0
0
1
R/W: R
R
R
R
R
R
R
R/W
(SH7059F)
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
1
1
1
1
R/W: R
R
R
R
R
R
R
R
Bit: 7
6
5
4
3
2
1
0
—
—
—
—
—
—
— SDTRF
Initial value: 0
0
0
0
0
0
0
1
R/W: R
R
R
R
R
R
R
R/W
The status register (SDSR) is a 16-bit register that can be read from and written to by the CPU. SDSR output from TDO is
possible, but serial data cannot be written to SDSR via TDI. The SDTRF bit is output by means of a 1-bit shift. In the case
of a 2-bit shift, the SDTRF bit is first output, followed by a reserved bit.
SDSR is initialized by TRST signal input or in software standby mode, but is not initialized by a reset.
(SH7058SF)
Bits 15, 13, and 11 to 1 are always read as 0, and the write value should always be 0.
Bits 14 and 12 are always read as 1, and the write value should always be 1.
(SH7059F)
Bits 15 to 1—Reserved: Bits 15 to 12 and 7 to 1 are always read as 0, and the write value should always be 0. Bits 11 to 8
are always read as 1, and the write value should always be 1.
Bit 0—Serial Data Transfer Control Flag (SDTRF): Indicates whether H-UDI registers can be accessed by the CPU. The
SDTRF bit is reset by the TRST signal , but is not initialized by a reset.
Bit 0: SDTRF
0
1
Description
Serial transfer to SDDR has ended, and SDDR can be accessed
Serial transfer to SDDR in progress
(Initial value)
Rev.3.00 Mar. 12, 2008 Page 542 of 948
REJ09B0177-0300