SH7059 Datasheet, PDF (909/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

27. Power-Down State
27.3.2 Canceling Hardware Standby Mode
Hardware standby mode is canceled by means of the HSTBY pin and RES pin. When HSTBY is driven high while RES is
low, the clock oscillator starts running. The RES pin should be held low long enough for clock oscillation to stabilize.
When RES is driven high, power-on reset exception processing is started and a transition is made to the program execution
state.
27.3.3 Hardware Standby Mode Timing
Figure 27.2 shows sample pin timings for hardware standby mode. A transition to hardware standby mode is made by
driving the HSTBY pin low after driving the RES pin low. Hardware standby mode is canceled by driving HSTBY high,
waiting for clock oscillation to stabilize, then switching RES from low to high.
Oscillator
pulse
width t_RESW
Oscillation
settling time
+
pulse
width
Reset
exception
processing
Figure 27.2 Hardware Standby Mode Timing
27.4 Software Standby Mode
27.4.1 Transition to Software Standby Mode
To enter software standby mode, set the software standby bit (SSBY) to 1 in SBYCR, then execute the SLEEP instruction.
This LSI switches from the program execution state to software standby mode. In software standby mode, power
consumption is drastically reduced by halting all the functions in this LSI and stopping the internal power supply except
the on-chip RAM. The contents of the on-chip RAM are held as long as the given voltages are supplied. For details on the
register states of on-chip peripheral modules, see Appendix A.2, Register States in Reset and Power-Down States. For
details on the pin states, see Appendix B, Pin States.
27.4.2 Canceling Software Standby Mode
Software standby mode is canceled by a rising edge of the NMI pin or a power-on reset.
Cancellation by a rising edge of the NMI pin: When a rising edge of the NMI pin is detected, the internal power supply
and clock oscillation start, and the inside of the LSI is in the power-on reset state. The clock is supplied only to the
oscillation settling counter, which counts the oscillation stabilizing time, until the oscillation settles.
When the oscillation settling counter value reaches the given value, meaning that the clock has been stabilized, the clock is
supplied to the entire chip and the power-on reset state in this LSI is canceled. The CPU starts the power-on reset
processing.
Rev.3.00 Mar. 12, 2008 Page 819 of 948
REJ09B0177-0300