SH7059 Datasheet, PDF (313/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

11. Advanced Timer Unit-II (ATU-II)
• Bits 15 to 9—Reserved: These bits are always read as 0. The write value should always be 0.
• Bit 8—Overflow Flag 11 (OVF11): Status flag that indicates TCNT11 overflow.
Bit 8: OVF11
0
1
Description
[Clearing condition]
When OVF11 is read while set to 1, then 0 is written to OVF11
[Setting condition]
When the TCNT11 value overflows (from H'FFFF to H'0000)
(Initial value)
• Bits 7 to 2—Reserved: These bits are always read as 0. The write value should always be 0.
• Bit 1—Input Capture/Compare-Match Flag 11B (IMF11B): Status flag that indicates GR11B input capture or
compare-match.
Bit 1: IMF11B
0
1
Description
[Clearing condition]
When IMF11B is read while set to 1, then 0 is written to IMF11B
(Initial value)
[Setting conditions]
• When the TCNT11 value is transferred to GR11B by an input capture signal while
GR11B is functioning as an input capture register
• When TCNT11 = GR11B while GR11B is functioning as an output compare register
• Bit 0—Input Capture/Compare-Match Flag 11A (IMF11A): Status flag that indicates GR11A input capture or
compare-match.
Bit 0: IMF11A
0
1
Description
[Clearing condition]
When IMF11A is read while set to 1, then 0 is written to IMF11A
(Initial value)
[Setting conditions]
• When the TCNT11 value is transferred to GR11A by an input capture signal while
GR11A is functioning as an input capture register
• When TCNT11 = GR11A while GR11A is functioning as an output compare register
Rev.3.00 Mar. 12, 2008 Page 223 of 948
REJ09B0177-0300