SH7059 Datasheet, PDF (291/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

11. Advanced Timer Unit-II (ATU-II)
• Bits 6 to 4—I/O Control 11B2 to 11B0 (IO11B2 to IO11B0): These bits select the general register (GR) function.
Bit 6:IO11B2
0
1
Bit 5:IO11B1
0
1
0
Bit 4:IO11B0
0
1
0
1
0
1
Description
GR is an output
compare register
GR is an input
capture register
1
0
1
Compare-match disabled; pin output
undefined
(Initial value)
0 output on GR compare-match
1 output on GR compare-match
Toggle output on GR compare-match
Input capture disabled
Input capture in GR on rising edge at TIO11B
pin (GR cannot be written to)
Input capture in GR on falling edge at TIO11B
pin (GR cannot be written to)
Input capture in GR on both rising and falling
edges at TIO11B pin (GR cannot be written
to)
• Bit 3—Reserved: This bit is always read as 0. The write value should always be 0.
• Bits 2 to 0—I/O Control 11A2 to 11A0 (IO11A2 to IO11A0): These bits select the general register (GR) function.
Bit 2:IO11A2
0
1
Bit 1:IO11A1
0
1
0
Bit 0:IO11A0
0
1
0
1
0
1
Description
GR is an output
compare register
GR is an input
capture register
1
0
1
Compare-match disabled; pin output
undefined
(Initial value)
0 output on GR compare-match
1 output on GR compare-match
Toggle output on GR compare-match
Input capture disabled
Input capture in GR on rising edge at TIO11A
pin (GR cannot be written to)
Input capture in GR on falling edge at TIO11A
pin (GR cannot be written to)
Input capture in GR on both rising and falling
edges at TIO11A pin (GR cannot be written
to)
Rev.3.00 Mar. 12, 2008 Page 201 of 948
REJ09B0177-0300