SH7059 Datasheet, PDF (29/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Differences between SH7058 and SH7058S/SH7059
SH7058 (Rev.3, REJ09B0046-0300H)
SH7058S/SH7059
19.4.3 H-UDI Reset
724
20.4.3 H-UDI Reset
Desciption added
• In software standby mode
19.5.2 Notes on Use
725
20.5.2 Notes on Use
5 to 10 added
20.2.1 Pin Descriptions
Pin Functions in RAM Monitor Mode
733
Description of AUDCK pin
The external clock input pin. Input the clock to be used for
debugging to this pin. The input frequency must not exceed
10 MHz. When no connection is made, this pin is pulled up
internally.
21.2.1 Pin Descriptions
Pin Functions in RAM Monitor Mode
Description amended
Description of AUDCK pin
The external clock input pin. Input the clock to be used for
debugging to this pin. The input frequency must not exceed
1/8 of the internal operating frequency(φ). When no
connection is made, this pin is pulled up internally.
20.3.2 Operation
Figure 20.2 Example of Data Output (32-Bit Output)
734
21.3.2 Operation
Figure 21.2 Example of Data Output (32-Bit Output)*
Title amended and note added
Note: * For details on the AUD reset timing and the timing
in branch trace mode, refer to section 29.3.13, AUD timing.
20.4.3 Operation
Figure 20.5 Example of Read Operation (Byte Read)
Figure 20.6 Example of Write Operation (Longword Write)
Figure 20.7 Example of Error Occurrence (Longword Read)
736,737
21.4.3 Operation
Figure 21.5 Example of Read Operation (Byte Read)*
Figure 21.6 Example of Write Operation (Longword Write)*
Figure 21.7 Example of Error Occurrence (Longword
Read)*
Title amended and note added
Note: * For details on the AUD reset timing and the timing
in branch trace mode, refer to section 29.3.13, AUD timing.
20.5.1 Initialization
737
3. When AUDRST is driven low
4. When the AUDSRST bit is set to 1 in the SYSCR1
register (see section 25.2.2)
5. When the MSTOP3 bit is set to 1 in the SYSCR2 register
(see section 25.2.3)
21.5.1 Initialization
Description added and amended
3. In software standby mode
4. When AUDRST is driven low
5. When the AUDSRST bit is set to 1 in the SYSCR1
register (see section 27.2.2)
6. When the MSTOP3 bit is set to 1 in the SYSCR2 register
(see section 27.2.3)
20.5.2 Operation in Software Standby Mode
737
21.5.2 Operation in Software Standby Mode
Deleted
Rev.3.00 Mar. 12, 2008 Page xxix of xc
REJ09B0177-0300