SH7059 Datasheet, PDF (770/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

24. ROM (SH7058S)
Table 24.10 Software Protection
Item
Protection by the SCO bit
Protection by FKEY
Emulation protection
Description
Clearing the SCO bit in FCCS disables
downloading of the programming/erasing
program, thus making the LSI enter a
programming/erasing-protected state.
Downloading and programming/erasing are
disabled unless the required key code is
written in FKEY. Different key codes are used
for downloading and for programming/erasing.
Setting the RAMS bit in RAMER to 1 makes
the LSI enter a programming/erasing-
protected state.
Function to be Protected
Download
Programming/
Erasure
O
O
O
O
O
O
24.6.3 Error Protection
Error protection is a mechanism for aborting programming or erasure when an error occurs, in the form of the
microcomputer getting out of control during programming/erasing of the flash memory or operations that are not in
accordance with the established procedures for programming/erasing. Aborting programming or erasure in such cases
prevents damage to the flash memory due to excessive programming or erasing.
If the microcomputer malfunctions during programming/erasing of the flash memory, the FLER bit in FCCS is set to 1 and
the LSI enters the error protection state, thus aborting programming or erasure.
The FLER bit is set to 1 in the following conditions:
• Flash memory is read during programming/erasing (including a vector read or an instruction fetch)
• When a SLEEP instruction is executed during programming/erasing
Error protection is cancelled (FLER bit is cleared) by a power-on reset, in software standby mode, or in hardware-standby
mode.
Note that the reset signal should only be released after providing a reset input over a period longer than the normal 100 μs.
Since high voltages are applied during programming/erasing of the flash memory, some voltage may still remain even
after the error protection state has been entered. For this reason, it is necessary to reduce the risk of damage to the flash
memory by extending the reset period so that the charge is released.
The state-transition diagram in figure 24.16 shows transitions to and from the error protection state.
Rev.3.00 Mar. 12, 2008 Page 680 of 948
REJ09B0177-0300