SH7059 Datasheet, PDF (158/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

6. Exception Processing
Table 6.4 Calculating Exception Processing Vector Table Addresses
Exception Source
Vector Table Address Calculation
Resets
Vector table address = (vector table address offset)
= (vector number) × 4
Address errors, interrupts, instructions
Vector table address = VBR + (vector table address offset)
= VBR + (vector number) × 4
Notes: 1. VBR: Vector base register
2. Vector table address offset: See table 6.3.
3. Vector number: See table 6.3.
6.2 Resets
6.2.1 Types of Reset
A reset is the highest-priority exception processing source. There are two kinds of reset, power-on and manual. As shown
in table 6.5, the CPU state is initialized in both a power-on reset and a manual reset. On-chip peripheral module registers
are also initialized by a power-on reset, but not by a manual reset.
Table 6.5 Exception Source Detection and Exception Processing Start Timing
Type
Power-on reset
Manual reset
Conditions for Transition to
Reset State
RES
Low
High
High
WDT Overflow
—
Power-on reset
Manual reset
CPU/MULT/
FPU/INTC
Initialized
Initialized
Initialized
Internal States
On-Chip eripheral
Modules
PFC, IO Port
Initialized
Initialized
Initialized
Not initialized
Not initialized
Not initialized
6.2.2 Power-On Reset
Power-On Reset by Means of RES Pin: When the RES pin is driven low, the chip enters the power-on reset state. To
reliably reset the chip, the RES pin should be kept at the low level for at least the duration of the oscillation settling time at
power-on or when in standby mode (when the clock is halted), or at least 10 t_cyc when the clock is running. In the power-on
reset state, the CPU's internal state and all the on-chip peripheral module registers are initialized.
In the power-on reset state, power-on reset exception processing starts when the RES pin is first driven low for a set period
of time and then returned to high. The CPU operates as follows:
1. The initial value (execution start address) of the program counter (PC) is fetched from the exception processing vector
table.
2. The initial value of the stack pointer (SP) is fetched from the exception processing vector table.
3. The vector base register (VBR) is cleared to H'00000000 and the interrupt mask bits (I3-I0) of the status register (SR)
are set to H'F (1111).
4. The values fetched from the exception processing vector table are set in the PC and SP, and the program begins
executing.
Be certain to always perform power-on reset processing when turning the system power on.
Rev.3.00 Mar. 12, 2008 Page 68 of 948
REJ09B0177-0300