SH7059 Datasheet, PDF (94/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

1. Overview
Item
Advanced timer unit-II
(ATU-II)
Advanced pulse controller
(APC)
Watchdog timer (WDT)
(1 channel)
Compare-match timer
(CMT)
(2 channels)
Serial communication
interface (SCI)
(5 channels)
Synchronous serial
communication unit (SSU)
(2 channels)
Controller area network-II
(HCAN-II)
(2 channels)
Features
• Maximum 65 inputs or outputs can be processed
⎯ Four 32-bit input capture inputs
⎯ Thirty 16-bit input capture inputs/output compare outputs
⎯ Sixteen 16-bit one-shot pulse outputs
⎯ Eight 16-bit PWM outputs
⎯ Six 8-bit event counters
⎯ One gap detection function
• I/O pin output inversion function
• Maximum eight pulse outputs on reception of ATU-II (channel 11)
compare-match signal
• Can be switched between watchdog timer and interval timer function
• Internal reset, external signal, or interrupt generated by counter overflow
• Two kinds of internal reset
⎯ Power-on reset
⎯ Manual reset
• Selection of 4 counter input clocks
• A compare-match interrupt can be requested independently for each channel
• Selection of asynchronous or synchronous mode
• Simultaneous transmission/reception (full-duplex) capability
• Serial data communication possible between multiple processors (asynchronous mode)
• Clock inversion function
• LSB-/MSB-first selection function for transmission
• Support for master mode
• Synchronous serial communications with devices having a different clock phase or polarity
• Choice of 8/16/32-bit width of transmit/receive data
• Full-duplex communication capability
• Continuous serial communications
• Choice of LSB-first or MSB-first transfer
• Choice of clock source from among seven internal clocks
• Five interrupt sources
• CAN version: Bosch 2.0B active compatible
• Buffer size (per channel): Transmit/receive × 31, receive-only × 1
• Receive message filtering capability
Rev.3.00 Mar. 12, 2008 Page 4 of 948
REJ09B0177-0300