SH7059 Datasheet, PDF (723/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

23.8 Port G
Port G is an input/output port with the four pins shown in figure 23.7.
23. I/O Ports (I/O)
Port G
PG3 (I/O) /IRQ3 (input) /ADTRG0 (input)
PG2 (I/O) /IRQ2 (input) /ADEND (output)
PG1 (I/O) /IRQ1 (input)
PG0 (I/O) /PULS7 (output) /HRxD0 (input) /HRxD1 (input)
Figure 23.7 Port G
23.8.1 Register Configuration
The port G register configuration is shown in table 23.13.
Table 23.13 Register Configuration
Name
Port G data register
Abbreviation
R/W
PGDR
R/W
Initial Value
H'0000
Address
H'FFFFF764
Access Size
8, 16
23.8.2 Port G Data Register (PGDR)
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit: 7
6
5
4
3
2
1
0
—
—
—
—
PG3 PG2 PG1 PG0
DR
DR
DR
DR
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R/W R/W R/W R/W
The port G data register (PGDR) is a 16-bit readable/writable register that stores port G data. Bits PG3DR to PG0DR
correspond to pins PG3/IRQ3/ADTRG0 to PG0/PULS7/HRxD0/HRxD1.
When a pin functions as a general output, if a value is written to PGDR, that value is output directly from the pin, and if
PGDR is read, the register value is returned directly regardless of the pin state.
When a pin functions as a general input, if PGDR is read, the pin state, not the register value, is returned directly. If a
value is written to PGDR, although that value is written into PGDR, it does not affect the pin state. Table 23.14
summarizes port G data register read/write operations.
PGDR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in
software standby mode. It is not initialized in sleep mode.
• Bits 15 to 4—Reserved: These its are always read as 0. The write value should always be 0.
Rev.3.00 Mar. 12, 2008 Page 633 of 948
REJ09B0177-0300