SH7059 Datasheet, PDF (396/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

11. Advanced Timer Unit-II (ATU-II)
Internal data bus
H
CPU
Bus
interface
1st write operation
H
Module data
bus
TSTR2
TSTR1
TSTR3
Internal data bus
L
CPU
Bus
interface
2nd write operation
L
Module data bus
Figure 11.47 Write to TSTR1, TSTR2 and TSTR3
TSTR2
TSTR1
TSTR3
11.5.3 Registers Requiring 16-Bit Access
The free-running counters (TCNT; but excluding TCNT0, TCNT10A, TCNT10B, TCNT10D, and TCNT10H), the general
registers (GR; but excluding GR9A to GR9D), down-counters (DCNT), offset base register (OSBR), cycle registers
(CYLR), buffer registers (BFR), duty registers (DTR), timer connection register (TCNR), one-shot pulse terminate register
(OTR), down-count start register (DSTR), output compare registers (OCR: but excluding OCR10B), reload registers
(RLDR8, RLD10C), correction counter clear register (TCCLR10), timer interrupt enable register (TIER), and timer status
register (TSR) are 16-bit registers. These registers are connected to the CPU via an internal 16-bit data bus, and can be
read or written (read only, in the case of OSBR) a word at a time.
Figure 11.48 shows the operation when performing a word read or write access to TCNT1A.
CPU
Internal data bus
Bus
interface
Module data bus
Figure 11.48 TCNT1A Read/Write Operation
TCNT1A
11.5.4 8-Bit or 16-Bit Accessible Registers
The timer control registers (TCR1A, TCR1B, TCR2A, TCR2B, TCR6A, TCR6B, TCR7A, TCR7B), timer I/O control
registers (TIOR1A to TIOR1D, TIOR2A to TIOR2D, TIOR3A, TIOR3B, TIOR4A, TIOR4B, TIOR5A, TIOR5B), and the
timer start register (TSTR1, TSTR2, TSTR3) are 8-bit registers. These registers are connected to the CPU with the upper 8
bits or lower 8 bits of the internal 16-bit data bus, and can be read or written a byte at a time.
In addition, a pair of 8-bit registers for which only the least significant bit of the address is different, such as timer I/O
control register 1A (TIOR1A) and timer I/O control register 1B (TIOR1B), can be read or written in combination a word
at a time.
Figures 11.49 and 11.50 show the operation when performing individual byte read or write accesses to TIOR1A and
TIOR1B. Figure 11.51 shows the operation when performing a word read or write access to TIOR1A and TIOR1B
simultaneously.
Rev.3.00 Mar. 12, 2008 Page 306 of 948
REJ09B0177-0300