SH7059 Datasheet, PDF (593/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

18. A/D Converter
The operation of the A/D converter after ADF is set to 1 differs between single mode and scan mode.
In single mode, after the A/D converter transfers the digit value to ADDR, ADF is set to 1 and the A/D converter
enters the idle state. In scan mode, ADF is set to 1 after all the set conversions end. For example, in the case of 8-
channel scanning, ADF is set to 1 immediately after the end of conversion for AN28 to AN31 (group 7). After ADF is
set to 1, conversion continues in the case of continuous scanning, and ends in the case of single-cycle scanning.
Note that 1 cannot be written to ADF.
• Bit 6—A/D Interrupt Enable (ADIE): Enables or disables the A/D interrupt (ADI).
To prevent incorrect operation, ensure that the ADST bit in A/D control register 2 (ADCR2) is cleared to 0 before
switching the operating mode.
Bit 6:ADIE
0
1
Description
A/D interrupt (ADI2) is disabled
A/D interrupt (ADI2) is enabled
(Initial value)
When A/D conversion ends and the ADF bit in ADCSR2 is set to 1, an A/D2 A/D interrupt (ADI2) will be generated If
the ADIE bit is 1. ADI2 is cleared by clearing ADF or ADIE to 0.
• Bits 5 and 4—A/D Mode 1 and 0 (ADM1, ADM0): These bits select the A/D conversion mode from single mode, 4-
channel scan mode,and 8-channel scan mode.
To prevent incorrect operation, ensure that the ADST bit in A/D control register 2 (ADCR2) is cleared to 0 before
switching the operating mode.
Bit 5:ADM1
0
1
Bit 4:ADM0
0
1
0
1
Description
Single mode
4-channel scan mode (analog groups 6 and 7)
8-channel scan mode (analog groups 6 and 7)
Reserved
(Initial value)
When ADM1 and ADM0 are set to 00, single mode is set. In single mode, operation ends after A/D conversion has
been performed once on the analog channels selected with bits CH2 to CH0 in ADCSR.
When ADM1 and ADM0 are set to 01, 4-channel scan mode is set. In scan mode, A/D conversion is performed
continuously on a number of channels. The channels on which A/D conversion is to be performed in scan mode are set
with bits CH2 to CH0 in ADCSR2. In 4-channel scan mode, conversion is performed continuously on the channels in
one of analog groups 6 (AN24 to AN27) or 7 (AN28 to AN31).
When the ADCS bit is cleared to 0, selecting scanning of all channels within the group (AN24 to AN27, AN28 to
AN31), conversion is performed continuously, once only for each channel within the group, and operation stops on
completion of conversion for the last (highest-numbered) channel.
When ADM1 and ADM0 are set to 10, 8-channel scan mode is set. In 8-channel scan mode, conversion is performed
continuously on the 8 channels in analog groups 6 (AN24 to AN27) and 7 (AN28 to AN31). When the ADCS bit is
cleared to 0, selecting scanning of all channels within the groups (AN24 to AN31), conversion is performed
continuously, once only for each channel within the groups, and operation stops on completion of conversion for the
last (highest-numbered) channel.
For details of the operation in single mode and scan mode, see section 18.4, Operation.
• Bit 3—Reserved: This bit is always read as 1. The write value should always be 0.
• Bits 2 to 0—Channel Select 2 to 0 (CH2 to CH0): These bits, together with the ADM1 and ADM0 bits, select the
analog input channels.
To prevent incorrect operation, ensure that the ADST bit in A/D control register 2 (ADCR2) is cleared to 0 before
changing the analog input channel selection.
Rev.3.00 Mar. 12, 2008 Page 503 of 948
REJ09B0177-0300