SH7059 Datasheet, PDF (289/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

TIOR3B, TIOR4B, TIOR5B
Bit:
Initial value:
R/W:
Note: x = 3 to 5
7
CCIxD
0
R/W
6
IOxD2
0
R/W
5
IOxD1
0
R/W
4
IOxD0
0
R/W
11. Advanced Timer Unit-II (ATU-II)
3
CCIxC
0
R/W
2
IOxC2
0
R/W
1
IOxC1
0
R/W
0
IOxC0
0
R/W
TIOR3A, TIOR3B, TIOR4A, TIOR4B, TIOR5A, and TIOR5B specify whether general registers GR3A to GR3D, GR4A
to GR4D, and GR5A to GR5D are used as input capture or compare-match registers, and also perform edge detection and
output value setting. They also select enabling or disabling of free-running counter (TCNT3 to TCNT5) clearing on
compare-match.
Each TIOR is initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode.
• Bit 7—Clear Counter Enable Flag 3B, 4B, 5B, 3D, 4D, 5D (CCI3B, CCI4B, CCI5B, CCI3D, CCI4D, CCI5D): These
bits select enabling or disabling of free-running counter (TCNT) clearing.
Bit 7: CCIxx
Description
0
TCNT clearing disabled
1
TCNT cleared on GR compare-match
Note: xx = 3B, 4B, 5B, 3D, 4D, or 5D
(Initial value)
TCNT is cleared on compare-match only when GR is functioning as an output compare register.
• Bits 6 to 4—I/O Control 3B2 to 3B0, 4B2 to 4B0, 5B2 to 5B0, 3D2 to 3D0, 4D2 to 4D0, 5D2 to 5D0 (IO3B2 to
IO3B0, IO4B2 to IO4B0, IO5B2 to IO5B0, IO3D2 to IO3D0, IO4D2 to IO4D0, IO5D2 to IO5D0): These bits select
the general register (GR) function.
Bit 6:IOxx2
0
Bit 5:IOxx1
0
Bit 4:IOxx0
0
1
1
0
1
1
0
0
1
1
0
1
Note: xx = 3B, 4B, 5B, 3D, 4D, or 5D
Description
GR is an output
compare register
GR is an input
capture register
(input capture by
channel 3 and 9
compare-match
enabled)
Compare-match disabled; pin output
undefined
(Initial value)
0 output on GR compare-match
1 output on GR compare-match
Toggle output on GR compare-match
Input capture disabled (In channel 3 only, GR
cannot be written to)
Input capture in GR on rising edge at TIOxx
pin (GR cannot be written to)
Input capture in GR on falling edge at TIOxx
pin (GR cannot be written to)
Input capture in GR on both rising and falling
edges at TIOxx pin (GR cannot be written to)
Rev.3.00 Mar. 12, 2008 Page 199 of 948
REJ09B0177-0300