SH7059 Datasheet, PDF (41/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Differences between SH7058 and SH7058S/SH7059
SH7058 (Rev.3, REJ09B0046-0300H)
22.9.1 Register Configuration
Table 22.15 Register Configuration
822
Note: Register access with an internal clock multiplication
ratio of 4 requires four or five internal clock (φ) cycles.
22.9.2 Port H Data Register (PHDR)
822
PHDR is initialized to H'0000 by a power-on reset
(excluding a WDT power-on reset), and in hardware
standby mode. It is not initialized in software standby mode
or sleep mode.
22.10.1 Register Configuration
Table 22.17 Register Configuration
824
Note: Register access with an internal clock multiplication
ratio of 4 requires four or five internal clock (φ) cycles.
22.10.2 Port J Data Register (PJDR)
824
PJDR is initialized to H'0000 by a power-on reset
(excluding a WDT power-on reset), and in hardware
standby mode. It is not initialized in software standby mode
or sleep mode.
22.11.1 Register Configuration
Table 22.19 Register Configuration
826
Note: Register access with an internal clock multiplication
ratio of 4 requires four or five internal clock (φ) cycles.
22.11.2 Port K Data Register (PKDR)
827
PKDR is initialized to H'0000 by a power-on reset
(excluding a WDT power-on reset), and in hardware
standby mode. It is not initialized in software standby mode
or sleep mode.
22.12 Port L
Figure 22.11 Port L
828
PL13 (I/O) / IRQOUT (output)
PL12 (I/O) / IRQ4 (input)
PL7 (I/O) / SCK2 (I/O)
SH7058S/SH7059
23.9.1 Register Configuration
Table 23.15 Register Configuration
Note deleted
23.9.2 Port H Data Register (PHDR)
Description amended
PHDR is initialized to H'0000 by a power-on reset
(excluding a WDT power-on reset), in hardware standby
mode, and in software standby mode. It is not initialized in
sleep mode.
23.10.1 Register Configuration
Table 23.17 Register Configuration
Note deleted
23.10.2 Port J Data Register (PJDR)
Description amended
PJDR is initialized to H'0000 by a power-on reset
(excluding a WDT power-on reset), in hardware standby
mode, and in software standby mode. It is not initialized in
sleep mode.
23.11.1 Register Configuration
Table 23.19 Register Configuration
Note deleted
23.11.2 Port K Data Register (PKDR)
Description amended
PKDR is initialized to H'0000 by a power-on reset
(excluding a WDT power-on reset), in hardware standby
mode, and in software standby mode. It is not initialized in
sleep mode.
23.12 Port L
Figure 23.11 Port L
Pin name added
PL13 (I/O) / IRQOUT (output) / SCS1 (I/O)
PL12 (I/O) / IRQ4 (input) / SCS0 (I/O)
PL7 (I/O) / SCK2 (I/O) / SSCK1 (output)
22.12.1 Register Configuration
Table 22.21 Register Configuration
828
Note: Register access with an internal clock multiplication
ratio of 4 requires four or five internal clock (φ) cycles.
23.12.1 Register Configuration
Table 23.21 Register Configuration
Note deleted
Rev.3.00 Mar. 12, 2008 Page xli of xc
REJ09B0177-0300