SH7059 Datasheet, PDF (317/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

11. Advanced Timer Unit-II (ATU-II)
• Bit 2—Input Capture/Compare-Match Interrupt Enable 1C (IME1C): Enables or disables interrupt requests by IMF1C
in TSR1A when IMF1C is set to 1.
Bit 2: IME1C
0
1
Description
IMI1C interrupt requested by IMF1C is disabled
IMI1C interrupt requested by IMF1C is enabled
(Initial value)
• Bit 1—Input Capture/Compare-Match Interrupt Enable 1B (IME1B): Enables or disables interrupt requests by IMF1B
in TSR1A when IMF1B is set to 1.
Bit 1: IME1B
0
1
Description
IMI1B interrupt requested by IMF1B is disabled
IMI1B interrupt requested by IMF1B is enabled
(Initial value)
• Bit 0—Input Capture/Compare-Match Interrupt Enable 1A (IME1A): Enables or disables interrupt requests by IMF1A
in TSR1A when IMF1A is set to 1.
Bit 0: IME1A
0
1
Description
IMI1A interrupt requested by IMF1A is disabled
IMI1A interrupt requested by IMF1A is enabled
(Initial value)
TIER1B: TIER1B controls enabling/disabling of channel 1 compare-match and overflow interrupt requests.
Bit:
15
14
13
12
11
10
9
—
—
—
—
—
—
—
Initial value:
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R
8
OVE1B
0
R/W
Bit:
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
CME1
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R
R/W
• Bits 15 to 9—Reserved: These bits are always read as 0. The write value should always be 0.
• Bit 8—Overflow Interrupt Enable 1B (OVE1B): Enables or disables interrupt requests by OVF1B in TSR1B when
OVF1B is set to 1.
Bit 8: OVE1B
0
1
Description
OVI1B interrupt requested by OVF1B is disabled
OVI1B interrupt requested by OVF1B is enabled
(Initial value)
• Bits 7 to 1—Reserved: These bits are always read as 0. The write value should always be 0.
Rev.3.00 Mar. 12, 2008 Page 227 of 948
REJ09B0177-0300