SH7059 Datasheet, PDF (514/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

17. Controller Area Network-II (HCAN-II)
(2) Mailboxes
The mailboxes are message buffers which are configured of RAM. There are 32 mailboxes, and each mailbox stores
the following information.
• CAN message control (StdID, RTR, DLC, IDE, etc.)
• CAN message data (for CAN data frames)
• Local acceptance filter mask (LAFM) during reception
• 3-bit mailbox configuration, automatic transmit bit for remote request, and new message control bit
(3) Mailbox Control
The mailbox control handles the following functions.
For receive messages, compares the IDs, generates appropriate RAM addresses to store messages from the CAN
interface into the mailbox, and sets/clears corresponding registers.
To transmit messages, runs the internal arbitration to select the correct priority message which is event-triggered, loads
the message from the mailbox into the Tx-buffer of the CAN interface, and sets/clears corresponding registers
accordingly.
Arbitrates mailbox accesses between the host CPU and the CAN interface or mailbox control.
Contains registers such as TXPR, TXCR, TXACK, ABACK, RXPR, RFPR, and MBIMR.
(4) Timer
The timer is a block which transmits and receives messages at a specific time frame and records the result. The timer is
a 16-bit free-running up counter which is controlled by the host CPU. It provides three 16-bit compare match registers.
They can generate interrupt signals, set or clear the counter value in the local offset value, and clear messages in the
transmission queue. Two 16-bit input capture registers are included to record timestamps on CAN messages and
synchronize the timer value globally within a CAN system.
The clock period of this timer offers a wide selection generated from the peripheral clock.
Contains registers such as TCNTR, TCR, TPSR, TDCR, LOSR, ICR0_tm, ICR0_cc, ICR0_buf, ICR1, TCMR0,
TCMR1, TCMR2, TMR, CCR, CCR_buf, and CMAX.
[Important] The SH7059 and SH7058S do not support the timer function.
(5) CAN Interface
The CAN interface supports the requirements for a CAN bus data link controller which is specified in Reference 2
(section 17.1). It fulfils all the functions of a data link layer (DLC layer) as specified by the 7 layers of the OSI model.
This block provides the receive error counter, transmit error counter, and bit timing set registers, and various test
modes corresponding to the CAN bus specification. This block also stores transmit/receive data for the CAN data link
controller.
17.2.3 Pin Configuration
Table 17.1 lists the pin configuration and functions.
Table 17.1 Pin Configuration
Name
HRxD0
HTxD0
HRxD1
HTxD1
Input/Output
Input
Output
Input
Output
Function
CAN bus receive signal of channel 0
CAN bus transmit signal of channel 0
CAN bus receive signal of channel 1
CAN bus transmit signal of channel 1
Rev.3.00 Mar. 12, 2008 Page 424 of 948
REJ09B0177-0300