SH7059 Datasheet, PDF (906/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

27. Power-Down State
• Bit 5— Software Standby Flag (SSBYF)
This bit is set to 1 by a transition to software standby mode. It is cleared to 0 by a transition to hardware standby mode
or a power-on reset by the RES pin. When software standby mode is cancelled by a rising edge of the NMI signal, this
bit is not cleared to 0.
This is a read-only bit and cannot be modified.
Bit 5: SSBYF
0
1
Description
Indicates that software standby mode has not been entered or it has been initialized by a power-on
reset after a transition to software standby mode.
(Initial value)
After a transition to software standby mode, the bit has not been initialized by a power-on reset.
• Bits 4 to 0—Reserved: These bits are always read as 1. The write value should always be 1.
27.2.2 System Control Register 1 (SYSCR1)
Bit:
7
—
Initial value:
0
R/W:
R
6
5
4
3
2
1
0
—
—
—
—
— AUDSRST RAME
0
0
0
0
0
0
1
R
R
R
R
R
R/W
R/W
System control register 1 (SYSCR1) is an 8-bit readable/writable register that performs AUD software reset control and
enables or disables access to the on-chip RAM.
SYSCR1 is initialized to H'01 by a power-on reset (at the rising edge).
• Bits 7 to 2—Reserved: These bits are always read as 0. The write value should always be 0.
• Bit1— AUD Software Reset (AUDSRST): This bit controls AUD reset using software. Setting AUDSRST bit to 1
places the AUD module in the power-on reset state.
Bit 1: AUDSRST
0
1
Description
AUD reset state cleared
AUD reset state entered
(Initial value)
• Bit 0—RAME Enable (RAME): Selects enabling or disabling of the on-chip RAM. When RAME is set to 1, on-chip
RAM is enabled. When RAME is cleared to 0, on-chip RAM cannot be accessed. In this case, a read or instruction
fetch from on-chip RAM will return an undefined value, and a write to on-chip RAM will be ignored. The initial value
of RAME is 1.
When on-chip RAM is disabled by clearing RAME to 0, do not place an instruction that attempts to access on-chip RAM
immediately after the SYSCR1 write instruction, as normal access cannot be guaranteed in this case.
When on-chip RAM is enabled by setting RAME to 1, place an SYSCR1 read instruction immediately after the SYSCR1
write instruction. Normal access cannot be guaranteed if an on-chip RAM access instruction is placed immediately after
the SYSCR1 write instruction.
Bit 0: RAME
0
1
Description
On-chip RAM disabled
On-chip RAM enabled
(Initial value)
Rev.3.00 Mar. 12, 2008 Page 816 of 948
REJ09B0177-0300