SH7059 Datasheet, PDF (447/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

15. Serial Communication Interface (SCI)
15.2 Register Descriptions
15.2.1 Receive Shift Register (RSR)
Bit:
7
6
5
4
3
2
1
0
R/W:
–
–
–
–
–
–
–
–
The receive shift register (RSR) receives serial data. Data input at the RxD pin is loaded into RSR in the order received,
LSB (bit 0) first, converting the data to parallel form. When one byte has been received, it is automatically transferred to
RDR.
The CPU cannot read or write to RSR directly.
15.2.2 Receive Data Register (RDR)
Bit:
7
6
5
4
3
2
1
0
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R
R
The receive data register (RDR) stores serial receive data. The SCI completes the reception of one byte of serial data by
moving the received data from the receive shift register (RSR) into RDR for storage. RSR is then ready to receive the next
data. This double buffering allows the SCI to receive data continuously.
The CPU can read but not write to RDR. RDR is initialized to H'00 by a power-on reset, and in hardware standby mode
and software standby mode. It is not initialized by a manual reset.
15.2.3 Transmit Shift Register (TSR)
Bit:
7
6
5
4
3
2
1
0
R/W:
–
–
–
–
–
–
–
–
The transmit shift register (TSR) transmits serial data. The SCI loads transmit data from the transmit data register (TDR)
into TSR, then transmits the data serially from the TxD pin, LSB (bit 0) first. After transmitting one data byte, the SCI
automatically loads the next transmit data from TDR into TSR and starts transmitting again. If the TDRE bit of SSR is 1,
however, the SCI does not load the TDR contents into TSR.
The CPU cannot read or write to TSR directly.
15.2.4 Transmit Data Register (TDR)
Bit:
7
6
5
4
3
2
1
0
Initial value:
1
1
1
1
1
1
1
1
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Rev.3.00 Mar. 12, 2008 Page 357 of 948
REJ09B0177-0300