SH7059 Datasheet, PDF (589/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

18. A/D Converter
• Bit 6—A/D Interrupt Enable (ADIE): Enables or disables the A/D interrupt (ADI).
To prevent incorrect operation, ensure that the ADST bit in A/D control registers 0 and 1 (ADCR0, ADCR1) is cleared
to 0 before switching the operating mode.
Bit 6:ADIE
0
1
Description
A/D interrupt (ADI0, ADI1) is disabled
A/D interrupt (ADI0, ADI1) is enabled
(Initial value)
When A/D conversion ends and the ADF bit is set to 1, an A/D0 or A/D1 A/D interrupt (ADI0, ADI1) will be
generated If the ADIE bit is 1. ADI0 and ADI1 are cleared by clearing ADF or ADIE to 0.
• Bits 5 and 4: A/D Mode 1 and 0 (ADM1, ADM0): These bits select the A/D conversion mode from single mode, 4-
channel scan mode, 8-channel scan mode, and 12-channel scan mode.
To prevent incorrect operation, ensure that the ADST bit in A/D control registers 1 and 0 (ADCR1, ADCR0) is cleared
to 0 before switching the operating mode.
Bit 5:ADM1
0
1
Bit 4:ADM0
0
1
0
1
Description
Single mode
4-channel scan mode (analog groups 0, 1, 2, 3, 4, 5)
8-channel scan mode (analog groups 0, 1, 3, 4)
12-channel scan mode (analog groups 0, 1, 2, 3, 4, 5)
(Initial value)
When ADM1 and ADM0 are set to 00, single mode is set. In single mode, operation ends after A/D conversion has
been performed once on the analog channels selected with bits CH3 to CH0 in ADCSR.
When ADM1 and ADM0 are set to 01, 4-channel scan mode is set. In scan mode, A/D conversion is performed
continuously on a number of channels. The channels on which A/D conversion is to be performed in scan mode are set
with bits CH3 to CH0 in ADCSR1 and ADCSR0. In 4-channel scan mode, conversion is performed continuously on
the channels in one of analog groups 0 (AN0 to AN3), 1 (AN4 to AN7), 2 (AN8 to AN11), 3 (AN12 to AN15, 4
(AN16 to AN19), or 5 (AN20 to AN23).
When the ADCS bit is cleared to 0, selecting scanning of all channels within the group (AN0 to AN3, AN4 to AN7,
AN8 to AN11, or AN12 to AN15, AN16 to AN19, AN20 to AN23), conversion is performed continuously, once only
for each channel within the group, and operation stops on completion of conversion for the last (highest-numbered)
channel.
When ADM1 and ADM0 are set to 10, 8-channel scan mode is set. In 8-channel scan mode, conversion is performed
continuously on the 8 channels in analog groups 0 (AN0 to AN3) and 1 (AN4 to AN7) or analog groups 3 (AN12 to
AN15) and 4 (AN16 to AN19). When the ADCS bit is cleared to 0, selecting scanning of all channels within the
groups (AN0 to AN7 or AN12 to AN19), conversion is performed continuously, once only for each channel within the
groups, and operation stops on completion of conversion for the last (highest-numbered) channel.
When ADM1 and ADM0 are set to 11, 12-channel scan mode is set. In 12-channel scan mode, conversion is
performed continuously on the 12 channels in analog groups 0 (AN0 to AN3), 1 (AN4 to AN7), and 2 (AN8 to AN11)
or analog groups 3 (AN12 to AN15), 4 (AN16 to AN19), and 5 (AN20 to AN23). When the ADCS bit is cleared to 0,
selecting scanning of all channels within the groups (AN0 to AN11 or AN12 to AN19), conversion is performed
continuously, once only for each channel within the groups, and operation stops on completion of conversion for the
last (highest-numbered) channel.
For details of the operation in single mode and scan mode, see section 18.4, Operation.
• Bits 3 to 0—Channel Select 3 to 0 (CH3 to CH0): These bits, together with the ADM1 and ADM0 bits, select the
analog input channels.
To prevent incorrect operation, ensure that the ADST bit in A/D control registers 1 and 0 (ADCR1, ADCR0) is cleared
to 0 before changing the analog input channel selection.
Rev.3.00 Mar. 12, 2008 Page 499 of 948
REJ09B0177-0300