SH7059 Datasheet, PDF (548/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

17. Controller Area Network-II (HCAN-II)
• RXPR1n (n = 0, 1)
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXPR1[15:0]
Initial Value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/
WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1
Bit
15 to 0
Bit Name Initial Value R/W Description
RXPR1[15:0] 0
R/WC1 Set receive mailboxes corresponding to mailboxes 31 to 16 respectively.
0: Clearing condition: Writing 1
1: Corresponding mailbox has received a CAN data frame
Setting condition: Completion of data frame reception in corresponding
mailbox
• RXPR0n (n = 0, 1)
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXPR0[15:0]
Initial Value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/
WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1
Bit
15 to 0
Bit Name Initial Value R/W Description
RXPR0[15:0] 0
R/WC1 Set receive mailboxes corresponding to mailboxes 15 to 0 respectively.
0: Clearing condition: Writing 1
1: Corresponding mailbox has received a CAN data frame
Setting condition: Completion of data frame reception in corresponding
mailbox
17.5.6 Remote Request Register n (RFPR1n, RFPR0n) (n = 0, 1)
RFPR1 and RFPR0 are 16-bit readable/conditionally-writable registers. RFPR is a register that contains the remote request
flags associated with the receive mailboxes. When a CAN remote frame is successfully stored in a receive mailbox, the
corresponding bit is set in RFPR. The corresponding bit is cleared by writing 1. Writing 0 is ignored. There is a bit for all
mailboxes. However, the bit is only set if the mailbox is set by its MBC (mailbox configuration) to receive remote frames.
When an RFPR bit is set, IRR2 (remote frame request interrupt flag) is also set if its MBIMR (mailbox interrupt mask
register) is not set, and the interrupt signal is generated if IMR2 is not set. These bits are only set by receiving remote
frames and not by receiving data frames.
If a data frame is overwritten/overrun with a remote frame or vice versa, UMSR, RXPR, and RFPR will be set for the
same mailbox. In this case the application needs to check the RTR bit within the mailbox control field to understand the
nature of the message on the mailbox. Consequently when UMSR is set, both RXPR and RFPR should be checked and, if
necessary, cleared.
Rev.3.00 Mar. 12, 2008 Page 458 of 948
REJ09B0177-0300