SH7059 Datasheet, PDF (532/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

17. Controller Area Network-II (HCAN-II)
17.4.4 HCAN-II_Bit Configuration Register n (HCAN-II_BCR0_n, HCAN-II_BCR1_n)
(n = 0, 1)
The bit configuration registers (BCR0 and BCR1) are 16-bit readable/writable registers that set CAN bit timing parameters
and the baud rate prescaler for the CAN interface.
For the following description the following definition is used:
Timequanta = ^BRP
f_clk
Where: BRP (baud rate predivider) is stored in BCR0 and fclk is Pφ (peripheral clock).
• BCR1
For details on TSEG1 and TSEG2 settings, see table 17.5.
Bit: 15 14 13 12 11 10 9 8 7
TSEG1[3:0]
TSEG2[2:0]
Initial Value: 0 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W ⎯ R/W R/W R/W ⎯
6543
SJW[1:0]
0000
⎯ R/W R/W ⎯
210
EG BSP
000
⎯ R/W R/W
Bit
Bit Name Initial Value R/W Description
15
TSEG1[3] 0
R/W Time Segment 1 (TSEG1[3:0] = BCR1[15:12])
14
TSEG1[2] 0
13
TSEG1[1] 0
12
TSEG1[0] 0
R/W Set the segment for absorbing output buffer, CAN bus, and input buffer
R/W ^{delay. A value from 4 to 16 time quanta can be set.}
R/W ^{0000: Setting prohibited}
0001: Setting prohibited
0010: Setting prohibited
0011: PRSEG + PHSEG1 = 4 time quanta
0100: PRSEG + PHSEG1 = 5 time quanta
:
1111: PRSEG + PHSEG1 = 16 time quanta
11
—
0
— Reserved
The write value should be 0. The read value is not guaranteed.
10
TSEG2[2] 0
R/W Time Segment 2 (TSEG2[2:0] = BCR1[10:8])
9
TSEG2[1] 0
8
TSEG2[0] 0
R/W Set the segment for correcting 1-bit time error. A value from 2 to 8 time
R/W ^{quanta can be set.}
000: Setting prohibited
001: PHSEG2 = 2 time quanta (setting prohibited depending on the condition
so see table 16.5)
010: PHSEG2 = 3 time quanta
011: PHSEG2 = 4 time quanta
100: PHSEG2 = 5 time quanta
101: PHSEG2 = 6 time quanta
110: PHSEG2 = 7 time quanta
111: PHSEG2 = 8 time quanta
7, 6
—
0
— Reserved
The write value should be 0. The read value is not guaranteed.
Rev.3.00 Mar. 12, 2008 Page 442 of 948
REJ09B0177-0300