SH7059 Datasheet, PDF (550/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

17. Controller Area Network-II (HCAN-II)
• MBIMR1n (n = 0, 1)
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MBIMR1[15:0]
Initial Value: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
15 to 0
Bit Name Initial Value R/W
MBIMR1[15: 1
R/W
0]
Description
Enable or disable interrupts requests from individual mailbox 31 to mailbox
16 respectively.
0: Interrupt request from IRR1/IRR2/IRR8/
IRR9 enabled
1: Interrupt request from IRR1/IRR2/IRR8/
IRR9 disabled
• MBIMR0n (n = 0, 1)
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MBIMR0[15:0]
Initial Value: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
15 to 0
Bit Name Initial Value R/W
MBIMR0[15: 1
R/W
0]
Description
Enable or disable interrupt requests from individual mailbox 15 to mailbox 0
respectively.
0: Interrupt request from IRR1/IRR2/IRR8/
IRR9 enabled
1: Interrupt request from IRR1/IRR2/IRR8/
IRR9 disabled
17.5.8 Unread Message Status Register n (UMSR1n, UMSR0n) (n = 0, 1)
UMSR1 and UMSR0 are 16-bit readable/writable registers that record the receive mailboxes whose contents have not
been accessed by the host CPU prior to a new message being received. If the host CPU has not cleared the corresponding
bit in RXPR/RFPR when a new message for a mailbox is received, the corresponding UMSR bit is set. This bit is cleared
by writing 1. Writing 0 is ignored.
If a mailbox is set for transmission, the corresponding UMSR bit cannot be set.
• UMSR1n (n = 0, 1)
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UMSR1[15:0]
Initial Value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/
WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1
Rev.3.00 Mar. 12, 2008 Page 460 of 948
REJ09B0177-0300