SH7059 Datasheet, PDF(17/1042 Page) Renesas Technology Corp – 32-Bit RISC Microcomputer

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SH7059 Datasheet, PDF (17/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

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Differences between SH7058 and SH7058S/SH7059

SH7058 (Rev.3, REJ09B0046-0300H)

Table 10.2 Selecting On-Chip Peripheral Module Request

Modes with the RS Bits

180, 181

RS4 RS3 RS2

000

1

10

1

DMAC

Transfer

Request

RS1 RS0 Source

0 1 SCI0

transmit

block

1 0 SCI0

receive

block

1 SCI1

transmit

block

0 0 SCI1

receive

block

1 SCI2

transmit

block

1 0 SCI2

receive

block

1 SCI3

transmit

block

0 0 SCI3

receive

block

1 SCI4

transmit

block

1 0 SCI4

receive

block

1 A/D0

0 0 A/D1

1 A/D2

1 1 HCAN0

DMAC Transfer

Request Signal

Transfer

Source

Transfer

Destination Bus Mode

TXI0 (SCI0 transmit- Donât care* TDR0

data-empty transfer

request)

Burst/cycle-

steal

RXI0 (SCI0 receive-

data-full transfer

request)

RDR0

Donât care* Burst/cycle-

steal

TXI1 (SCI1 transmit- Donât care* TDR1

data-empty transfer

request)

Burst/cycle-

steal

RXI1 (SCI1 receive-

data-full transfer

request)

RDR1

Donât care* Burst/cycle-

steal

TXI2 (SCI2 transmit- Donât care* TDR2

data-empty transfer

request)

Burst/cycle-

steal

RXI2 (SCI2 receive-

data-full transfer

request)

RDR2

Donât care* Burst/cycle-

steal

TXI3 (SCI3 transmit- Donât care* TDR3

data-empty transfer

request)

Burst/cycle-

steal

RXI3 (SCI3 receive-

data-full transfer

request)

RDR3

Donât care* Burst/cycle-

steal

TXI4 (SCI4 transmit- Donât care* TDR4

data-empty transfer

request)

Burst/cycle-

steal

RXI4 (SCI4 receive-

data-full transfer

request)

RDR4

Donât care* Burst/cycle-

steal

ADI0 (A/D0

conversion end

interrupt)

ADDR0â

ADDR11

Donât care* Burst/cycle-

steal

ADI1 (A/D1

conversion end

interrupt)

ADDR12â Donât care* Burst/cycle-

ADDR23

steal

ADI2 (A/D2

conversion end

interrupt)

ADDR24â Donât care* Burst/cycle-

ADDR31

steal

RM0 (HCAN0

receive interrupt)

MB0âMB15 Donât care* Burst/cycle-

steal

DMAC

Transfer

Request

RS4 RS3 RS2 RS1 RS0 Source

1 0 0 0 1 ATU-II

1 0 ATU-II

1 ATU-II

1 0 0 ATU-II

1 ATU-II

1 0 ATU-II

1 ATU-II

1 0 0 0 ATU-II

1 ATU-II

1 0 ATU-II

1 ATU-II

1 0 0 ATU-II

DMAC Transfer

Request Signal

ICI0A (ICR0A input

capture generation)

ICI0B (ICR0B input

capture generation)

ICI0C (ICR0C input

capture generation)

ICI0D (ICR0D input

capture generation)

CMI6A (CYLR6A

compare-match

generation)

CMI6B (CYLR6B

compare-match

generation)

CMI6C (CYLR6C

compare-match

generation)

CMI6D (CYLR6D

compare-match

generation)

CMI7A (CYLR7A

compare-match

generation)

CMI7B (CYLR7B

compare-match

generation)

CMI7C (CYLR7C

compare-match

generation)

CMI7D (CYLR7D

compare-match

generation)

Transfer

Source

Donât care*

Donât care*

Donât care*

Donât care*

Donât care*

Transfer

Destination

Donât care*

Donât care*

Donât care*

Donât care*

Donât care*

Bus Mode

Burst/cycle-

steal

Burst/cycle-

steal

Burst/cycle-

steal

Burst/cycle-

steal

Burst/cycle-

steal

Donât care* Donât care* Burst/cycle-

steal

Donât care* Donât care* Burst/cycle-

steal

Donât care* Donât care* Burst/cycle-

steal

Donât care* Donât care* Burst/cycle-

steal

Donât care* Donât care* Burst/cycle-

steal

Donât care* Donât care* Burst/cycle-

steal

Donât care* Donât care* Burst/cycle-

steal

SH7058S/SH7059

Table 10.2 Selecting On-Chip Peripheral Module Request

Modes with the RS Bits

Table and legend amended

SSU0 transmit block, SSU0 receive block, SSU1 transmit

block, and SSU1 receive block added.

Legend:

Description of SSU0,SSU1 added

DMAC Transfer DMAC Transfer

RS4 RS3 RS2 RS1 RS0 Request Source Request Signal

Transfer

Source

0

0

0

0

1

SCI0 transmit block TXI0 (SCI0 transmit- Don't care*

data-empty transfer

request)

1

0

SCI0 receive block RXI0 (SCI0 receive-data- RDR0

full transfer request)

1

SCI1 transmit block TXI1 (SCI1 transmit- Don't care*

data-empty transfer

request)

1

0

0

SCI1 receive block RXI1 (SCI1 receive-data- RDR1

full transfer request)

1

SCI2 transmit block TXI2 (SCI2 transmit- Don't care*

data-empty transfer

request)

1

0

SCI2 receive block RXI2 (SCI2 receive-data- RDR2

full transfer request)

1

SCI3 transmit block TXI3 (SCI3 transmit- Don't care*

data-empty transfer

request)

1

0

0

0

SCI3 receive block RXI3 (SCI3 receive-data- RDR3

full transfer request)

1

SCI4 transmit block TXI4 (SCI4 transmit- Don't care*

data-empty transfer

request)

1

0

SCI4 receive block RXI4 (SCI4 receive-data- RDR4

full transfer request)

1

A/D0

ADI0 (A/D0

ADDR0â

conversion end interrupt) ADDR11

1

0

0

A/D1

ADI1 (A/D1

ADDR12â

conversion end interrupt) ADDR23

1

A/D2

ADI2 (A/D2

ADDR24â

conversion end interrupt) ADDR31

Transfer

Destination

TDR0

Don't care*

TDR1

Don't care*

TDR2

Don't care*

TDR3

Don't care*

TDR4

Don't care*

Don't care*

Don't care*

Don't care*

Bus Mode

Cycle-steal

Cycle-steal

Cycle-steal

Cycle-steal

Cycle-steal

Cycle-steal

Cycle-steal

Cycle-steal

Cycle-steal

Cycle-steal

Burst/cycle-

steal

Burst/cycle-

steal

Burst/cycle-

steal

1

0

SSU0 transmit block SSTSI0 (transmit-

Don't care* SSTDR0_0 to Cycle-steal

data-empty or

SSTDR3_0

transmit-end transfer

request of SSU0)

1

HCAN0

RM0 (HCAN0

receive interrupt)

MB0-MB31 Don't care*

Burst/cycle-

steal

1

0

0

0

0

SSU0 receive block SSRXI0 (receive-data- SSRDR0_0 to Don't care*

Cycle-steal

full transfer request of SSRDR3_0

SSU0)

1

ATU-II

1

0

ATU-II

ICI0A (ICR0A input

capture generation)

ICI0B (ICR0B input

capture generation)

Don't care*

Don't care*

Don't care*

Don't care*

Burst/cycle-

steal

Burst/cycle-

steal

1

ATU-II

1

0

0

ATU-II

ICI0C (ICR0C input

capture generation)

ICI0D (ICR0D input

capture generation)

Don't care*

Don't care*

Don't care*

Don't care*

Burst/cycle-

steal

Burst/cycle-

steal

1

ATU-II

CMI6A (CYLR6A

compare-match

generation)

Don't care* Don't care*

Burst/cycle-

steal

DMAC Transfer DMAC Transfer

RS4 RS3 RS2 RS1 RS0 Request Source Request Signal

Transfer

Source

Transfer

Destination

Bus Mode

1

0

1

1

0

ATU-II

CMI6B (CYLR6B

compare-match

generation)

Don't care* Don't care*

Burst/cycle-

steal

1

ATU-II

CMI6C (CYLR6C

compare-match

generation)

Don't care* Don't care*

Burst/cycle-

steal

1

0

0

0

ATU-II

CMI6D (CYLR6D

compare-match

generation)

Don't care* Don't care*

Burst/cycle-

steal

1

ATU-II

CMI7A (CYLR7A

compare-match

generation)

Don't care* Don't care*

Burst/cycle-

steal

1

0

ATU-II

CMI7B (CYLR7B

compare-match

generation)

Don't care* Don't care*

Burst/cycle-

steal

1

ATU-II

CMI7C (CYLR7C

compare-match

generation)

Don't care* Don't care*

Burst/cycle-

steal

1

0

0

ATU-II

CMI7D (CYLR7D

compare-match

generation)

Don't care* Don't care*

Burst/cycle-

steal

1

SSU1 transmit block SSTSI1 (transmit-

Don't care* SSTDR0_1 to Cycle-steal

data-empty or

SSTDR3_1

transmit-end transfer

request of SSU1)

1

0

SSU1 receive block SSRXI1 (receive-data- SSRDR0_1 to Don't care*

Cycle-steal

full transfer request of SSRDR3_1

SSU1)

Rev.3.00 Mar. 12, 2008 Page xvii of xc

REJ09B0177-0300

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