SH7059 Datasheet, PDF (225/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

10. Direct Memory Access Controller (DMAC)
• Bits 20–16—Resource Select 4–0 (RS4–RS0): These bits specify the transfer request source.
Bit 20: RS4
0
Bit 19: RS3
0
Bit 18: RS2
0
Bit 17: RS1
0
1
1
0
1
1
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
1
1
0
1
Notes: *1 Refer to no. 12 in section 10.5, Usage Notes.
*2 SSU: Synchronous Serial Communication Unit
Bit 16: RS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Description
No request*¹ (Initial value)
SCI0 transmission
SCI0 reception
SCI1 transmission
SCI1 reception
SCI2 transmission
SCI2 reception
SCI3 transmission
SCI3 reception
SCI4 transmission
SCI4 reception
On-chip A/D0
On-chip A/D1
On-chip A/D2
SSU0 transmission*²
HCAN0 (RM0)
SSU0 reception*²
ATU-II (ICI0A)
ATU-II (ICI0B)
ATU-II (ICI0C)
ATU-II (ICI0D)
ATU-II (CMI6A)
ATU-II (CMI6B)
ATU-II (CMI6C)
ATU-II (CMI6D)
ATU-II (CMI7A)
ATU-II (CMI7B)
ATU-II (CMI7C)
ATU-II (CMI7D)
SSU1 transmission*²
SSU1 reception*²
Auto-request
Rev.3.00 Mar. 12, 2008 Page 135 of 948
REJ09B0177-0300