SH7059 Datasheet, PDF (58/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Differences between SH7058 and SH7058S/SH7059
SH7058 (Rev.3, REJ09B0046-0300H)
Figure 23.20 Switching between User MAT and User Boot
MAT
889
Procedure for switching to the user boot MAT
(3) Execute four NOP instructions before accessing the
user boot MAT.
SH7058S/SH7059
Figure 25.20 Switching between User MAT and User Boot
MAT
Figure amended
Procedure for switching to the user boot MAT
(3) Execute eight NOP instructions before accessing the
user boot MAT.
Procedure for switching to the user MAT
(3) Execute four NOP instructions before accessing the
user MAT.
Procedure for switching to the user MAT
(3) Execute eight NOP instructions before accessing the
user MAT.
23.8.2 Interrupts during Programming/Erasing
(2) Interrupts during programming/erasing
892, 893
1. When flash memory is being programmed or erased,
both the user MAT and user boot MAT cannot be
accessed. Prepare the interrupt vector table and interrupt
processing routine in on-chip RAM or external memory.
Make sure the flash memory being programmed or erased
is not accessed by the interrupt processing routine. If flash
memory is read, the read values are not guaranteed. If the
relevant bank in flash memory that is being programmed or
erased is accessed, the error protection state is entered,
and programming or erasing is aborted. If a bank other
than the relevant bank is accessed, the error protection
state is not entered but the read values are not guaranteed.
25.8.2 Interrupts during Programming/Erasing
(2) Interrupts during programming/erasing
Description amended
1. When flash memory is being programmed or erased,
both the user MAT and user boot MAT cannot be
accessed. Prepare the interrupt vector table and interrupt
processing routine in on-chip RAM or external memory.
Make sure the flash memory being programmed or erased
is not accessed by the interrupt processing routine. If flash
memory is read, the read values are not guaranteed. If .
flash memory that is being programmed or erased is
accessed, the error protect state is entered, and
programming or erasing is aborted. .
5. When a transition is made to sleep mode or software
standby mode in the interrupt processing routine, the error
protection state is entered and programming/erasing is
aborted.
If a transition is made to the reset state, the reset signal
should only be released after providing a reset input over a
period longer than the normal 100 μs to reduce the
damage to flash memory.
5. When a transition is made to sleep mode in the
interrupt processing routine, the error protection state is
entered and programming/erasing is aborted.
If a transition is made to the reset state, the reset signal
should only be released after providing a reset input over a
period longer than the normal 100 μs to reduce the
damage to flash memory.
Rev.3.00 Mar. 12, 2008 Page lviii of xc
REJ09B0177-0300