SH7059 Datasheet, PDF (101/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

1. Overview
Type
Clock
System control
Operating mode
control
Interrupts
Pin No.
Symbol
FP-256H
BP-272
I/O Name
Function
PLLV_CC
60
A17
Input PLL power On-chip PLL oscillator power supply.
supply
For power supply connection, see section
5, Clock Pulse Generator (CPG).
PLLV_SS
62
A18
Input PLL ground On-chip PLL oscillator ground.
For power supply connection, see section
5, Clock Pulse Generator (CPG).
PLLCAP
61
B17
Input PLL
On-chip PLL oscillator external
capacitance capacitance connection pin.
For external capacitance connection, see
section 5, Clock Pulse Generator (CPG).
EXTAL
51
A14
Input External clock For connection to a crystal resonator. An
external clock source can also be
connected to the EXTAL pin.
XTAL
53
A15
Input/ Crystal
For connection to a crystal resonator.
output
CK
48
A13
Output Peripheral Supplies the peripheral clock to
clock
peripheral devices.
RES
58
B16
Input Power-on reset Executes a power-on reset when driven
low.
WDTOVF
124
BREQ
46
R17
Output Watchdog WDT overflow output signal.
timer overflow
C13
Input Bus request Driven low when an external device
requests the bus.
BACK
45
D12
Output Bus request Indicates that the bus has been granted
acknowledge to an external device. The device that
output the BREQ signal recognizes that
the bus has been acquired when it
receives the BACK signal.
MD0 to MD2 59, 55, 50
C16, C15, C14
Input
Mode setting
These pins determine the operating
mode. Do not change the input values
during operation.
HSTBY
57
A16
Input Hardware
When driven low, this pin forces a
standby
transition to hardware standby mode.
NMI
84
E20
Input Nonmaskable Nonmaskable interrupt request pin.
interrupt
Acceptance on the rising edge or falling
edge can be selected.
IRQ0 to IRQ7 169, 171, 173,
175, 230, 226,
217, 218
IRQOUT
231
V10, Y8, W9, W8, Input
K2, L3, P2, P1
Interrupt
requests
0 to 7
K1
Output Interrupt
request
output
Maskable interrupt request pins.
Level input or edge input can be selected.
Indicates that an interrupt has been
generated.
Enables interrupt generation to be
recognized in the bus-released state.
Rev.3.00 Mar. 12, 2008 Page 11 of 948
REJ09B0177-0300