SH7059 Datasheet, PDF (84/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 19 Multi-Trigger A/D Converter (MTAD).......................................................................... 517
19.1 Overview................................................................................................................................................................ 517
19.1.1 Feature ...................................................................................................................................................... 517
19.1.2 Block Diagram.......................................................................................................................................... 518
19.1.3 Input/Output Pins...................................................................................................................................... 519
19.1.4 Register Configuration.............................................................................................................................. 519
19.2 Register Descriptions ............................................................................................................................................. 520
19.2.1 A/D Trigger Control Registers 0 and 1 (ADTCR0 and ADTCR1)........................................................... 520
19.2.2 A/D Trigger Status Registers 0 and 1 (ADTSR0 and ADTSR1) .............................................................. 522
19.2.3 A/D Trigger Interrupt Enable Registers 0 and 1 (ADTIER0 and ADTIER1)........................................... 524
19.2.4 A/D Free-Running Counters (ADCNT0 and ADCNT1) .......................................................................... 526
19.2.5 A/D General Registers A and B (ADGR0A, ADGR0B, ADGR1A, and ADGR1B)................................ 526
19.2.6 A/D Cycle Registers 0 and 1 (ADCYLR0 and ADCYLR1)..................................................................... 527
19.2.7 A/D Duty Registers A and B (ADDR0A, ADDR0B, ADDR1A, and ADDR1B) .................................... 527
19.3 Operation ............................................................................................................................................................... 528
19.3.1 Overview................................................................................................................................................... 528
19.3.2 PWM Operation ........................................................................................................................................ 528
19.3.3 Compare Match Operation........................................................................................................................ 529
19.3.4 Multi-Trigger A/D Conversion Operation ................................................................................................ 529
19.3.5 Interrupts................................................................................................................................................... 533
19.3.6 Usage Notes .............................................................................................................................................. 533
19.3.7 Operation Waveform Examples................................................................................................................ 534
Section 20 High-performance User Debug Interface (H-UDI) ....................................................... 537
20.1 Overview................................................................................................................................................................ 537
20.1.1 Features..................................................................................................................................................... 537
20.1.2 H-UDI Block Diagram.............................................................................................................................. 538
20.1.3 Pin Configuration...................................................................................................................................... 539
20.1.4 Register Configuration.............................................................................................................................. 539
20.2 External Signals ..................................................................................................................................................... 540
20.2.1 Test Clock (TCK) ..................................................................................................................................... 540
20.2.2 Test Mode Select (TMS)........................................................................................................................... 540
20.2.3 Test Data Input (TDI) ............................................................................................................................... 540
20.2.4 Test Data Output (TDO) ........................................................................................................................... 540
20.2.5 Test Reset (TRST) .................................................................................................................................... 540
20.3 Register Descriptions ............................................................................................................................................. 541
20.3.1 Instruction Register (SDIR) ...................................................................................................................... 541
20.3.2 Status Register (SDSR)............................................................................................................................. 542
20.3.3 Data Register (SDDR) .............................................................................................................................. 543
20.3.4 Bypass Register (SDBPR) ........................................................................................................................ 543
20.3.5 Boundary scan register (SDBSR) ............................................................................................................. 543
20.3.6 ID code register (SDIDR) ......................................................................................................................... 555
20.4 Operation ............................................................................................................................................................... 556
20.4.1 TAP Controller ......................................................................................................................................... 556
20.4.2 H-UDI Interrupt and Serial Transfer......................................................................................................... 556
20.4.3 H-UDI Reset ............................................................................................................................................. 558
20.5 Boundary Scan ....................................................................................................................................................... 559
20.5.1 Supported Instructions .............................................................................................................................. 559
20.5.2 Notes on Use............................................................................................................................................. 560
20.6 Usage Notes ........................................................................................................................................................... 561
Rev.3.00 Mar. 12, 2008 Page lxxxiv of xc
REJ09B0177-0300