SH7059 Datasheet, PDF (208/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

9. Bus State Controller (BSC)
WCR is a 16-bit readable/writable register that specifies the number of wait cycles for each CS space.
WCR is initialized to H'7777 by a power-on reset, in hardware standby mode, and in software standby mode. It is not
initialized by a manual reset.
• Bit 15—Reserved
• Bits 14–12—CS3 Space Wait Specification (W32, W31, W30): These bits specify the number of waits for CS3 space
access.
Bit 14: W32
0
0
⋅⋅⋅
1
Bit 13: W31
0
0
1
Bit 12: W30
0
1
1
Description
No wait (external wait input disabled)
1 wait external wait input enabled
7 wait external wait input enabled
(Initial value)
• Bit 11—Reserved
• Bits 10–8—CS2 Space Wait Specification (W22, W21, W20): These bits specify the number of waits for CS2 space
access.
Bit 10: W22
0
0
⋅⋅⋅
1
Bit 9: W21
0
0
1
Bit 8: W20
0
1
1
Description
No wait (external wait input disabled)
1 wait external wait input enabled
7 wait external wait input enabled
(Initial value)
• Bit 7—Reserved
• Bits 6–4—CS1 Space Wait Specification (W12, W11, W10): These bits specify the number of waits for CS1 space
access.
Bit 6: W12
0
0
⋅⋅⋅
1
Bit 5: W11
0
0
1
Bit 4: W10
0
1
1
Description
No wait (external wait input disabled)
1 wait external wait input enabled
7 wait external wait input enabled
(Initial value)
• Bit 3—Reserved
• Bits 2–0—CS0 Space Wait Specification (W02, W01, W00): These bits specify the number of waits for CS0 space
access.
Bit 2: W02
0
0
⋅⋅⋅
1
Bit 1: W01
0
0
1
Bit 0: W00
0
1
1
Description
No wait (external wait input disabled)
1 wait external wait input enabled
7 wait external wait input enabled
(Initial value)
Rev.3.00 Mar. 12, 2008 Page 118 of 948
REJ09B0177-0300