SH7059 Datasheet, PDF (573/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

17. Controller Area Network-II (HCAN-II)
17.7.9 DMAC Interface
The HCAN-II can activate the DMAC when a message is received at mailbox 0 in channel 0. When an interrupt occurs by
mailbox 0 and the DMAC transfer ends after settings of the DMAC activation has been made, the RXPR0 and RFPR0
flags are cleared automatically. An interrupt request due to a receive interrupt from the HCAN-II cannot be sent to the
CPU in this case. Figure 17.13 shows a DMAC transfer flowchart. For details on the settings of the DMAC activation, see
section 10, Direct Memory Access Controller (DMAC).
Initial setting of DMAC
Set activation source
Set source and destination addresses
Set number of transmissions and interrupts
Receive a message at
mailbox 0 in channel 0
Activate DMAC
No
DMAC transfer ended?
Yes
Set DMAC transfer end bit
Clear RXPR and RFPR
: Processing by hardware
: Setting by user
Enable DMAC interrupt
No
Yes
Interrupt to CPU
Clear DMAC interrupt flag
End
Figure 17.13 DMAC Transfer Flowchart
Rev.3.00 Mar. 12, 2008 Page 483 of 948
REJ09B0177-0300