SH7059 Datasheet, PDF (740/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

24. ROM (SH7058S)
24.4 Register Configuration
24.4.1 Registers
The registers/parameters which control flash memory when the on-chip flash memory is valid are shown in table 24.4.
There are several operating modes for accessing flash memory, for example, read mode/program mode.
There are two memory MATs: user MAT and user boot MAT. The dedicated registers/parameters are allocated for each
operating mode and MAT selection. The correspondence of operating modes and registers/parameters for use is shown in
table 24.5.
Table 24.4 (1) Register Configuration
Name
Abbreviation*⁴
R/W
Initial Value Address
Access
Size
Flash code control status
register
FCCS
R, W*¹
H'00*²
H'80*²
H'FFFFE800 8
Flash program code select
register
FPCS
R/W
H'00
H'FFFFE801 8
Flash erase code select register FECS
R/W
H'00
H'FFFFE802 8
Flash key code register
FKEY
R/W
H'00
H'FFFFE804 8
Flash MAT select register
FMATS
R/W
H'00*³
H'AA*³
H'FFFFE805 8
Flash transfer destination
address register
FTDAR
R/W
H'00
H'FFFFE806 8
RAM emulation register
RAMER
R/W
H'0000
H'FFFFEC26 8, 16, 32
Notes:
All registers except for RAMER can be accessed only in bytes, and the access requires three cycles.
RAMER can be accessed in bytes or words, and the access requires three cycles.
1. The bits except the SCO bit are read-only bits. The SCO bit is a programming-only bit. (The value which can be
read is always 0.)
2. The initial value is H'00 when the FWE pin goes low.
The initial value is H'80 when the FWE pin goes high.
3. The initial value at initiation in user mode or user program mode is H'00.
The initial value at initiation in user boot mode is H'AA.
4. The registers except RAMER can be accessed only in bytes, and the access requires four cycles. Since the
RAMER register is in BSC, when it is accessed in bytes, the access requires four cycles, and when it is
accessed in longwords, the access requires eight cycles.
Rev.3.00 Mar. 12, 2008 Page 650 of 948
REJ09B0177-0300